Capacitor structure in a semiconductor device

A semiconductor device comprising:

• an integrated circuit formed on a substrate and divided into at least two dies arranged across an isolation barrier, the integrated circuit comprising:
• a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate;
• a thick passivation layer formed on the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics layers;
• a thick metal layer formed on the thick passivation layer;
• a plurality of isolator capacitors respectively formed of the thick metal layer and at least one metal layer in the interleaved inter-metal dielectric layers and interlayer dielectrics arranged as substantially parallel planes extending laterally with an overlap selected to compensate for dielectric leakage and fringe fields from creating voltage gradients, the plurality of isolator capacitors formed on separate dies from a single wafer whereby ratio of parasitic capacitance to primary capacitance is reduced;
• and
• a plurality of metal layers distributed within silicate glass dielectric layers, separated by thin silicon nitride layers and overlying inter-layer dielectric layers;
• the thick metal layer comprising a redistribution layer (RDL);
• and
• the thick passivation layer comprising an undoped silicate glass (USG) layer.

A method for forming a semiconductor device further comprising:

• forming a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics on a substrate;
• forming a thick passivation layer on the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics;
• forming a thick metal layer on the thick passivation layer;
• forming an integrated circuit on the substrate comprising a signal interface with at least one isolator capacitor;
• forming the at least one isolator capacitor comprising the thick passivation layer as an insulator whereby thickness of the thick passivation layer is selected greater than thickness sufficient for isolation so that testing for defects is eliminated;
• distributing the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics within silicate glass dielectric layers, separated by thin silicon nitride layers and overlying inter-layer dielectric layers;
• forming the thick passivation layer as an undoped silicate glass (USG) layer;
• and
• forming the thick metal layer as a redistribution layer (RDL).

A method for forming a semiconductor device further comprising:

• forming a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics on a substrate;
• forming a thick passivation layer on the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics;
• forming a thick metal layer on the thick passivation layer;
• forming an integrated circuit on the substrate comprising a signal interface with at least one isolator capacitor;
• forming the at least one isolator capacitor comprising the thick passivation layer as an insulator whereby thickness of the thick passivation layer is selected greater than thickness sufficient for isolation so that testing for defects is eliminated;
• dividing the integrated circuit into first and second dies;
• forming an isolation barrier between the first and second dies;
• forming a plurality of capacitors respectively on separate dies;
• configuring a converter in the first die to track process characteristics across the isolation barrier and modify amplitude of a fast differential edge modulation as a function of speed of an active device on a transmitting side of the isolation barrier;
• and
• configuring a differentiator in the second die to differentiate the fast differential edge modulation on a receiving side of the isolation barrier whereby differentiation bandwidth tracks slope rate of the differential edge modulation.