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US 7,732,878 B2Granted
MOS devices with continuous contact etch stop layer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsLiang-Gi Yao, Shiang-Bau Wang, Huan-Just Lin, Peng-Fu Hsu, Jin Ying, Hun-Jan Tao
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Abstract
A semiconductor structure includes a substrate, a gate stack on the substrate, a source/drain region adjacent the gate stack, a source/drain silicide region on the source/drain region, a protection layer on the source/drain silicide region, wherein a region over the gate stack is substantially free from the protection layer, and a contact etch stop layer (CESL) having a stress over the protection layer and extending over the gate stack.
Claims9
A semiconductor structure comprising:
- a substrate;
- a gate stack on the substrate;
- a gate silicide region in a top portion of the gate stack;
- a source region adjacent the gate stack;
- a source silicide region on the source region;
- a drain region adjacent and on an opposite side of the gate stack from the source region;
- a drain silicide region on the drain region, wherein the source and drain silicide regions have a substantially different thickness or a substantially different composition from the gate silicide region;
- a protection layer on the source and drain silicide regions, wherein the protection layer comprises a source portion directly over the source region, and a drain portion directly over the drain region;
- a contact etch stop layer (CESL) over the protection layer and extending over the gate silicide region;
- and
- a contact plug extending from over the CESL into the CESL, wherein the contact plug is in physical contact with the CESL, and not in physical contact with the protection layer.
8 more elements
A semiconductor structure comprising:
- a substrate;
- a PMOS device comprising:
- a first gate stack on the substrate;
- a first gate silicide region in a top portion of the first gate stack;
- a first source/drain region adjacent the first gate stack;
- a first source/drain silicide region on the first source/drain region;
- a first gate spacer on a sidewall of the first gate stack;
- and
- a protection layer over the first source/drain silicide region, wherein the region over the first gate stack is substantially free from the protection layer;
- an NMOS device comprising:
- a second gate stack on the substrate;
- a second gate spacer on a sidewall of the second gate stack, wherein a top surface of the protection layer is substantially leveled to a top surface of the first gate spacer and the second gate spacer;
- a second gate silicide region in a top portion of the second gate stack, wherein the first and the second gate silicide regions have substantially different compositions;
- a second source/drain region adjacent the second gate stack;
- and
- a second source/drain silicide region on the second source/drain region, wherein the protection layer is over the second source/drain silicide region, and wherein the region over the second gate stack is substantially free from the protection layer;
- and
- a contact etch stop layer (CESL) over the protection layer and the first and the second gate silicide regions.
15 more elements
Dependencies are inferred from the claim text.