Semiconductor device fabrication method and semiconductor device fabricated thereby
AssigneeKabushiki Kaisha Toshiba
InventorMasakatsu Tsuchiaki
Life of this patent
Estimating the term…
Abstract
A method of fabricating a semiconductor device having a pair of shallow silicided source and drain junctions with minimal leakage is disclosed. The semiconductor device typically has a MISFET structure with NiSi regions partially making up the source and drain regions. The fabrication method includes the steps of providing silicon surfaces having Si{110} crystal planes on both sides of this gate electrode and forming a plurality of nickel silicide (NiSi) regions, each having a rectangular planar shape whose shorter sides being equal or less than 0.5 μm in length and running along a Si<100> direction.
Claims11
A semiconductor device having a MISFET, comprising:
- a silicon substrate;
- a channel region of said MISFET in said silicon substrate;
- a gate insulating film on said channel region;
- a gate electrode overlying said channel region with said gate insulating film being sandwiched therebetween;
- a pair of spaced-apart source and drain regions interposing said channel region therebetween;
- and
- a plurality of nickel silicide regions making up part of said source and drain regions of said MISFET, said nickel silicide regions being provided on silicon surfaces having Si{110} crystal planes in said source and drain regions, and the each nickel silicide region containing a rectangular planar shape having long sides laying perpendicular to a Si<100> direction on said silicon surface and short sides being parallel to the Si<100> direction and having a width of 0.5 μm or less.
A semiconductor device having a fin type MISFET (“Fin MISFET”), comprising:
- a silicon substrate;
- a thin plate-shaped fin type single-crystalline silicon layer formed on said substrate;
- a channel region of said MISFET in said silicon layer;
- a gate insulating film on said channel region;
- a gate electrode overlying said channel region with said gate insulating film being sandwiched therebetween;
- a pair of spaced-apart source and drain regions interposing said channel region therebetween;
- and
- a plurality of nickel silicide regions making up part of said source and drain regions of said MISFET, said nickel silicide regions being provided on silicon surfaces having Si{110} crystal planes in said source and drain regions, and the each nickel silicide region containing a rectangular planar shape having long sides laying perpendicular to a Si<100> direction on said silicon surface and short sides being parallel to the Si<100> direction and having a width of 0.5 μm or less.
Dependencies are inferred from the claim text.