Grounding front-end-of-line structures on a SOI substrate
AssigneeInternational Business Machines Corporation
InventorsWilliam J. Cote, Oliver D. Patterson
Life of this patent
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AssigneeInternational Business Machines Corporation
InventorsWilliam J. Cote, Oliver D. Patterson
Estimating the term…
Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.
A structure comprising:
A method of grounding a silicon active region within a silicon-on-insulator (SOI) substrate prior to contact dielectric formation, the method comprising the steps of:
A structure for grounding a gate stack through a silicon-on-insulator (SOI) substrate, the structure comprising:
Dependencies are inferred from the claim text.