Gate metal routing for transistor with checkerboarded layout

A transistor comprising:

• a plurality of transistor segments organized into a plurality of sections, each transistor segment having a length and a width, the transistor segments of each section being arranged in a side-by-side relationship along the width, the sections being arranged in rows and columns, the sections of each row being arranged such that section-to-section the length of the transistor segments is alternately aligned in first and second lateral directions, the first lateral direction being substantially orthogonal to the second lateral direction, each transistor segment including:
• a pillar of a semiconductor material, the pillar having a source region disposed at or near a top surface;
• first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;
• first and second gate members respectively disposed on opposite sides of the pillar;
• and
• a first metal layer that includes a source bus coupled to the source region of each transistor segment, and a gate bus coupled to the first and second gate members of each transistor segment, the gate bus including top and bottom lines associated with each row, sections with the length of the segments aligned in the first lateral direction each having a first set of the first and second gate members coupled to the top line, and a second set of the first and second gate members coupled to the bottom line.

A transistor comprising:

• a plurality of transistor segments organized into a plurality of sections, each transistor segment having a length and a width, the transistor segments of each section being arranged in a side-by-side relationship along the width, the sections being arranged in rows and columns, the sections of each row being arranged such that section-to-section the length of the transistor segments is alternately aligned in first and second lateral directions, the first lateral direction being substantially orthogonal to the second lateral direction, each transistor segment including:
• a pillar of a semiconductor material formed in the shape of a closed loop, the pillar having a source region disposed at or near a top surface, a body region, and an extended drain region, the body region separating the source region from the extended drain region;
• first and second insulated gate members respectively disposed on opposite sides of the pillar adjacent the body region;
• a first metal layer that includes a source bus coupled to the source region of each transistor segment, and a gate bus coupled to the first and second gate members of each transistor segment, the gate bus including top and bottom lines associated with each row, the source bus extending continuously across each row between the top and bottom lines, and
• wherein sections with the length of the segments aligned in the first lateral direction each have a first set of the first and second gate members coupled to the top line, and a second set of the first and second gate members coupled to the bottom line.