US 7,732,855 B2Granted

Semiconductor memory device including recessed control gate electrode

AssigneeSamsung Electronics Co., Ltd.

InventorsSang-jin Park, Kwang-soo Seol, Yoon-dong Park, Sang-min Shin, In-jun Hwang, Sang-moo Choi, Ju-hee Park

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Abstract

A semiconductor memory device may include a semiconductor substrate, at least one control gate electrode, at least one storage node layer, at least one tunneling insulating layer, at least one blocking insulating layer, and/or first and second channel regions. The at least one control gate electrode may be recessed into the semiconductor substrate. The at least one storage node layer may be between a sidewall of the at least one control gate electrode and the semiconductor substrate. The at least one tunneling insulating layer may be between the at least one storage node layer and the at least one control gate electrode. The at least one blocking insulating layer may be between the storage node layer and the control gate electrode. The first and second channel regions may be between the at least one tunneling insulating layer and the semiconductor substrate to surround at least a portion of the sidewall of the control gate electrode and/or may be separated from each other.

Claims20

Dependent claims

A semiconductor memory device, comprising:

a semiconductor substrate;
at least one control gate electrode recessed into the semiconductor substrate;
at least one storage node layer between a sidewall of the at least one control gate electrode and a sidewall portion of the semiconductor substrate;
at least one tunneling insulating layer between the at least one storage node layer and the sidewall portion of the semiconductor substrate;
at least one blocking insulating layer between the at least one storage node layer and the at least one control gate electrode;
and
first and second channel regions between the at least one tunneling insulating layer and the sidewall portion of the semiconductor substrate;
wherein the first and second channel regions are separated from each other,
wherein the at least one blocking insulating layer has a dielectric constant greater than a dielectric constant of the at least one tunneling insulating layer, and
wherein for a given control gate electrode, the first and second channel regions are separated by a pair of separating insulating layers that face each other.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/808,982Filed 14 Jun 2007 · continuation in part
Priority: KR 10-2006-010156918 Oct 2006
Published: US 2008/0093662 A124 Apr 2008
Granted: 8 Jun 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10D 30/6891
Floating-gate IGFETs: characterised by the shapes, relative sizes or dispositions of the floating gate electrode
G11C 16/0408
Using variable threshold transistors, e.g. FAMOS: comprising cells containing floating gate transistors
H10D 30/0411
Of FETs having insulated gates [IGFET]: of FETs having floating gates
H10D 30/0413
Of FETs having insulated gates [IGFET]: of FETs having charge-trapping gate insulators, e.g. MNOS transistors

Family

Application11/709,860Parent of this continuation-in-part · filed 23 Feb 2007
US 2008/0093662 A1Pre-grant publication · published 24 Apr 2008
US 2007/0272973 A1Published application
US 8,148,767 B2Related patent
US 7,732,855 B2This patent

From the US filing history. Foreign family members aren’t listed.