Power semiconductor device with improved heat dissipation

A power semiconductor device, comprising:

• a semiconductor substrate having a first surface including an electrode contact area,
• a multi-layer circuitry structure formed above the first surface of the semiconductor substrate and including a power current conducting metallization layer,
• an electrode contact element formed of a first material having a relatively high electrical conductivity, the electrode contact element being in contact with at least a part of the electrode contact area of the first surface and being in contact with the power current conducting metallization layer,
• a dielectric layer formed of a second material having a heat conductivity of at least 10 W/(mK), and
• at least one blind contact element formed of the first material and in contact with the dielectric layer and in physical contact with the power current conducting metallization layer.

A power semiconductor device, comprising:

• a semiconductor substrate having a first surface including an electrode contact area,
• a multi-layer circuitry structure formed on the first surface of the semiconductor substrate and including a power current conducting metallization layer,
• an electrode contact element formed of a first material having a relatively high electrical conductivity, the electrode contact element being in contact with at least a part of the electrode contact area at the first surface and in contact with the power current conducting metallization layer,
• a dielectric layer formed of a second material, and
• at least one blind contact element formed of a third material which has a relatively high heat conductivity and is in contact with the dielectric layer and in physical contact with the power current conducting metallization layer adjacent to the electrode contact element.

A method of manufacturing a power semiconductor device, comprising:

• forming, on or above a semiconductor substrate having a first surface and comprising a gate structure and regions of different conductivity types for the power semiconductor device, a dielectric layer from a material having a heat conductivity of at least 10 W/(mK);
• etching through holes in the dielectric layer at positions that expose surface areas for electrode contact regions to be later implanted;
• forming electrode contact regions by implanting impurities into the semiconductor substrate via the through holes in the dielectric layer;
• forming an intermediate oxide layer on or above the dielectric layer;
• etching through holes in the intermediate oxide layer at first positions that correspond to the positions of the through holes in the dielectric layer, and at second positions adjacent to the first positions;
• forming contact elements from a material having a relatively high electrical conductivity and a relatively high heat conductivity mainly composed of W, in the through holes in the intermediate oxide layer;
• and
• forming a power current conducting metallization layer mainly composed of Cu or Al, and in physical contact with the contact elements.

A power semiconductor device comprising:

• a semiconductor substrate having a plurality of discrete doped wells disposed therein and an intervening surface between the respective discrete doped wells,
• a dielectric layer disposed above the semiconductor substrate,
• an intermediate oxide layer disposed above the dielectric layer,
• a power current conducting metallization layer disposed above the intermediate oxide layer, and
• at least one blind contact element vertically extending from the dielectric layer through the intermediate oxide layer to the power current conducting metallization layer and physically contacting the metallization layer, wherein the at least one blind contact element is located above the intervening surface between the respective doped wells, substantially comprises tungsten and has a heat conductivity that is significantly higher than the intermediate oxide layer.