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US 7,732,843 B2Granted
Solid state image sensor
AssigneePanasonic Corporation
InventorKeishi Tachikawa
Life of this patent
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Abstract
Forming an impurity region 6 and an impurity region 5 having a lower concentration than the impurity region 6 in a lower layer region of a gate electrode close to the boundary with a signal electron-voltage conversion section of a horizontal CCD outlet makes it possible to smooth a potential distribution at the time of transfer, improve the transfer efficiency, increase the number of saturated electrons and reduce variations in the transfer efficiency and variations in saturation.
Claims5
A solid-state image sensor comprising:
- an N-type semiconductor substrate;
- a P-type well formed in the N-type semiconductor substrate;
- an N-type horizontal transfer region formed in the P-type well;
- a gate insulating film formed on a surface of the N-type semiconductor substrate;
- a first storage gate electrode formed on a horizontal transfer outlet of the N-type horizontal transfer region via the gate insulating film;
- a first offset gate electrode formed on the horizontal transfer outlet via the gate insulating film which is next to the first storage gate electrode;
- a first P-type region in the N-type horizontal transfer region under the first offset gate electrode;
- and
- a first N-type region formed in the horizontal transfer region directly under the first offset gate electrode and the first storage gate electrode,
- wherein a concentration of an N-type impurity of the first N-type region is lower than a concentration of an N-type impurity of the N-type horizontal transfer region, wherein a bottom of the first N-type region is lower than a bottom of the N-type horizontal transfer region.
7 more elements
Dependencies are inferred from the claim text.