Structure and method for forming a planar schottky contact
AssigneeFairchild Semiconductor Corporation
InventorFred Session
Life of this patent
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Abstract
A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.
Claims29
A monolithically integrated trench FET and Schottky diode, comprising:
- a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer, a trench in the Schottky region having a dielectric layer lining the trench sidewalls and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench;
- and
- an interconnect layer electrically contacting the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.
A semiconductor structure, comprising:
- a first trench in a first region of a semiconductor layer, the first trench having a conductive electrode therein, wherein a top surface the conductive electrode is recessed relative to a top surface of the first region of the semiconductor layer;
- and
- a second trench in a second region of the semiconductor layer, the second trench having a conductive electrode therein, wherein the conductive electrode in the second trench has a top surface that is substantially coplanar with a top surface of the second region of the semiconductor layer,
- wherein a top surface of the first region of the semiconductor layer is higher than a top surface of the second region of the semiconductor layer.
A method of forming a monolithically integrated trench FET and Schottky diode, the method comprising:
- forming a plurality of wenches in a FET region and a Schottky region of a semiconductor layer;
- forming a recessed conductive electrode in each trench;
- and
- forming a contact opening in the Schottky region by removing at least a portion of the semiconductor layer and a portion of a recessed conductive electrode in a trench so that a top surface of the recessed conductive electrode and a top surface of the semiconductor layer in the Schottky region are substantially coplanar.
A method of forming a semiconductor structure, comprising:
- forming a plurality of trenches in a semiconductor layer;
- forming a first dielectric layer lining the trench sidewalls and bottom;
- forming a conductive electrode in each trench;
- forming a second dielectric layer over the semiconductor layer;
- forming a contact opening by removing a portion of the second dielectric layer, a portion of the semiconductor layer and a portion of each of one or more conductive electrodes in the plurality of trenches so that a top surface of the one or more conductive electrodes and a top surface of the semiconductor layer in the contact opening are substantially coplanar;
- and
- forming an interconnect layer electrically contacting the one or more conductive electrodes and the semiconductor layer through the contact opening such that the interconnect layer forms a Schottky contact with the semiconductor layer.
Dependencies are inferred from the claim text.