High selectivity etching process for metal gate N/P patterning

A method for fabricating an integrated circuit, wherein the integrated circuit includes a substrate, the method comprising:

• forming a first set of gate structures and a second set of gate structures over the substrate, wherein the first and second set of gate structures include an interfacial layer, a high-k dielectric layer, a first conductive layer, and a hard mask layer;
• partially removing the hard mask layer from the first set of gate structures utilizing a first dry etching process;
• treating a remaining portion of the hard mask layer in the first set of gate structures utilizing a second dry etching process;
• removing the remaining portion of the hard mask layer in the first set of gate structures utilizing a first wet etching process;
• and
• removing the hard mask layer from the second set of gate structures utilizing a second wet etching process.

A method for fabricating an integrated circuit, the method comprising:

• providing a substrate having a first region that includes at least one gate structure and a second region that includes at least one gate structure;
• forming an opening in the at least one gate structure of the first region and the at least one gate structure of the second region;
• forming an interfacial layer, a high-k dielectric layer, and a first conductive layer over the substrate, wherein the interfacial layer, high-k dielectric layer, and first conductive layer partially fill in the openings of the at least one gate structures of the first and second regions;
• forming a hard mask layer over the substrate, wherein the hard mask layer fills the remainder of the openings in the at least one gate structures of the first and second regions;
• removing a portion of the hard mask layer in the first region;
• treating a remaining portion of the hard mask layer in the first region;
• removing the remaining portion of the hard mask layer in the first region;
• removing the first conductive layer partially filling in the opening of the at least one gate structure of the first region;
• forming a second conductive layer in the opening of the at least one gate structure in the first region;
• and
• removing the hard mask layer in the second region.