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US 7,732,336 B2Granted
Shallow trench isolation process and structure with minimized strained silicon consumption
AssigneeGlobalfoundries Inc.
InventorsQi Xiang, James N. Pan, Jung-Suk Goo
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Abstract
A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a compound semiconductor layer above a box layer.
Claims10
A method of producing an integrated circuit, comprising:
- providing a buried oxide (BOX) layer;
- providing a compound semiconductor layer above the BOX layer;
- providing a strained semiconductor layer above the compound semiconductor layer;
- selectively etching trenches in the compound semiconductor layer;
- and
- providing isolation material in the trenches etched in the compound semiconductor layer, wherein the trenches include sidewalls, the sidewalls of the trenches being at least partially covered by the strained semiconductor layer;
- wherein the strained semiconductor material is silicon and the compound semiconductor material is silicon-germanium and the trenches extend from the strained semiconductor material at a top to the BOX layer at a bottom.
4 more elements
Dependencies are inferred from the claim text.