Interconnection structure of integrated circuit chip
AssigneeSamsung Electronics Co., Ltd.
InventorsSe-Young Jeong, Sung-Min Sim, Soon-Bum Kim, In-Young Lee, Young-Hee Song
Life of this patent
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Abstract
An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.
Claims16
A method of forming an interconnection structure, comprising:
- providing an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit;
- forming a passivation layer on a top surface of the IC chip to expose the terminal;
- forming a pad metal layer on the passivation layer;
- patterning the pad metal layer to form an input/output (I/O) pad including a first portion in contact with the terminal and a second portion that extends over the passivation layer;
- forming a polymer layer on the I/O pad and the passivation layer to expose a portion of the I/O pad;
- providing plating core particles on the portion of the (I/O) pad exposed through the polymer layer;
- and
- forming an electroless plating layer on the portion of the I/O pad exposed through the polymer layer.
A method of forming an interconnection structure, comprising:
- providing an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit;
- forming a passivation layer on a top surface of the IC chip to expose the terminal;
- forming a pad metal layer on the passivation layer;
- patterning the pad metal layer to form an inputloutput (I/O) pad including a first portion in contact with the terminal and a second portion that extends over the passivation layer;
- providing plating core particles on the I/O pad;
- and
- forming an electroless plating layer on the I/O pad.
Dependencies are inferred from the claim text.