Methods of forming contact structures for memory cells using both anisotropic and isotropic etching
AssigneeSamsung Electronics Co., Ltd.
InventorsHyun-Chul Shin, Jeong-Ho Park, Jung-Young Lee, Kwang-Won Park
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Abstract
Methods of forming a cell of a NOR-type flash memory device are provided in which a first gate pattern having a first sidewall and a second gate pattern having a second sidewall that opposes the first sidewall are formed on a semiconductor substrate. A source/drain region is formed in the semiconductor substrate between the first and second gate patterns. An etch stop layer is formed on the first and second sidewalls that defines a gap region. A dielectric layer is formed in the gap region, and is then etched to form a contact hole. Finally, a conductive material is deposited in the contact hole.
Claims26
A method of forming a contact structure for a memory device, comprising:
- forming first and second spaced apart gate patterns on a substrate;
- forming an etch stop layer on at least a first sidewall of the first gate pattern and a second sidewall of the second gate pattern, wherein the etch stop layer on the first and second sidewalls define a gap therebetween;
- forming an interlayer dielectric layer on the etch stop layer, the interlayer dielectric layer filling the gap;
- planarizing the interlayer dielectric layer;
- anisotropically etching the interlayer dielectric layer to form a preliminary contact hole in the interlayer dielectric layer that has a width that is narrower than a width of the gap;
- isotropically etching the interlayer dielectric layer to widen the preliminary contact hole to form a contact hole, wherein the isotropic etching of the interlayer dielectric layer exposes the etch stop layer in the gap;
- and
- depositing a conductive material in the contact hole to form a contact plug that is electrically connected to the substrate,
- wherein a width of an upper portion of the contact hole is larger than a width of a bottom portion of the contact hole;
- and
- wherein the anisotropic etch of the interlayer dielectric layer that forms the preliminary contact hole does not expose the etch stop layer and wherein a width of the preliminary contact hole is narrower than the width of the gap at the bottom of the gap.
A method of forming a contact for a memory device, the method comprising:
- forming a first gate pattern having a first sidewall and a second gate pattern having a second sidewall that opposes the first sidewall on a semiconductor substrate;
- forming a source/drain region in the semiconductor substrate between the first and second gate patterns;
- forming an etch stop layer on the first and second sidewalls, wherein the etch stop layer on the first sidewall and the etch stop layer on the second sidewall define a gap region that is located over the source/drain region;
- forming a dielectric layer in the gap region, the dielectric layer filling the gap;
- planarizing the dielectric layer;
- using an etch mask having an opening that is less than a width of the gap region to anisotropically etch the dielectric layer to form a preliminary contact hole that only partially penetrates through the dielectric layer;
- isotropically etching the sidewalls and a bottom portion of the preliminary contact hole to form the contact hole;
- and
- depositing a conductive material in the contact hole,
- wherein a width of an upper portion of the contact hole is larger than a width of a bottom portion of the contact hole, and
- wherein the anisotropic etch of the dielectric layer that forms the preliminary contact hole does not expose the etch stop layer, and wherein a width of the preliminary contact hole is narrower than a width of a portion of the gap region that is farthest from the etch mask.
Dependencies are inferred from the claim text.