Sidewall memory with self-aligned asymmetrical source and drain configuration

A method of forming a semiconductor structure, the method comprising:

• providing a semiconductor substrate;
• forming a gate stack comprising:
• forming a gate dielectric on the semiconductor substrate;
• and
• forming a control gate on the gate dielectric;
• forming a dielectric layer on the gate stack and the semiconductor substrate;
• patterning the dielectric layer to form two tunneling layers on opposite sides of the gate stack, wherein the tunneling layers each comprise a vertical portion on a sidewall of the gate stack and a horizontal portion on a top surface of the semiconductor substrate;
• tilt implanting an impurity into the semiconductor substrate to form a lightly doped source region and a lightly doped drain region, wherein the tilt implanting only tilts from a source side to a drain side;
• forming a storage layer after the step of forming the dielectric layer;
• patterning the storage layer to form storages, wherein each of the storages is on a horizontal portion of one of the tunneling layers;
• and
• implanting a source region and a drain region using the storages as masks;
• wherein the completed formed drain region including the lightly doped drain region is spaced apart from a respective edge of the control gate and at least a portion of the second tunneling layer overlies a portion of the semiconductor substrate free from impurities implanted during the tilt implanting and the implanting of the drain region.

A method of forming a memory cell, the method comprising:

• providing a semiconductor substrate;
• forming a gate stack comprising:
• forming a gate dielectric on the semiconductor substrate;
• and
• forming a control gate on the gate dielectric;
• forming tunneling layers on opposite side of the gate stack, wherein each of the tunneling layer comprises a vertical portion on a sidewall of the gate stack, and a horizontal portion on a top surface of the semiconductor substrate;
• forming storages, wherein each of the storages is on a horizontal portion of one of the tunneling layers;
• tilt implanting an impurity into the semiconductor substrate after the step of forming the storages to form a lightly doped source region and a lightly doped drain region, wherein the tilt implanting only tilts from a source side to a drain side, and wherein the lightly doped source region and the lightly doped drain region are both spaced apart from respective edges of the control gate;
• and
• implanting a source region and a drain region using the storages as masks.