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US 7,732,291 B2Granted
Semiconductor device having stressed etch stop layers of different intrinsic stress in combination with PN junctions of different design in different device regions
AssigneeGlobalfoundries Inc.
InventorsJoe Bloomquist, Peter Javorka, Manfred Horstmann, Gert Burbach
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Abstract
By selectively performing a pre-amorphization implantation process in logic areas and memory areas, the negative effect of the interaction between stressed overlayers and dislocation defects may be avoided or at least significantly reduced in the memory areas, thereby increasing production yield and stability of the memory areas.
Claims9
A method, comprising:
- performing a first pre-amorphization process of drain and source regions in at least one of first P-channel transistors and first N-channel transistors in a first device region, while masking second P-channel transistors and second N-channel transistors formed in a second device region of a semiconductor device, wherein said first device region comprises a logic region and said second device region comprises a memory region;
- performing a source/drain dopant implantation after performing said first pre-amorphization process;
- forming a stressed layer having a compressive stress over said first and second P-channel transistors;
- and
- forming a stressed layer having a tensile stress over said first and second N-channel transistors.
2 more elements
Dependencies are inferred from the claim text.