Method for fabricating a semiconductor structure

A method for fabricating a semiconductor structure, said method comprising:

• providing a semiconductor layer and a gate stack on the semiconductor layer, wherein the semiconductor layer comprises (i) a channel region directly beneath the gate stack, and (ii) first and second semiconductor regions essentially not covered by the gate stack, and wherein the channel region is disposed between the first and second semiconductor regions;
• removing the first and second semiconductor regions;
• doping regions directly beneath the removed first and second semiconductor regions so as to form first and second source/drain regions, respectively, such that top surfaces of the first and second source/drain regions are below a top surface of the channel region;
• providing an underlying dielectric layer wherein the semiconductor layer is on the underlying dielectric layer;
• implanting second dopants in a top layer of the underlying dielectric layer except in a separating dielectric region of the top layer directly beneath the gate stack;
• etching away the top layer of the underlying dielectric layer except the separating dielectric region;
• and
• epitaxially growing a semiconductor material to fill the removed top layer of the underlying dielectric layer before said removing the first and second semiconductor regions is performed.

A method for fabricating a semiconductor structure, said method comprising:

• providing (i) an underlying dielectric layer, (ii) a semiconductor layer on the underlying dielectric layer, and (iii) a gate stack on the semiconductor layer;
• implanting first dopants in a top layer of the underlying dielectric layer except in a separating dielectric region of the top layer directly beneath the gate stack;
• removing the top layer of the underlying dielectric layer except the separating dielectric region;
• epitaxially growing semiconductor regions to fill the removed top layer of the underlying dielectric layer;
• and
• implanting second dopants in semiconductor regions of the semiconductor layer and the epitaxially grown semiconductor regions on opposing sides of the gate stack so as to form first and second source/drain regions such that the separating dielectric region is disposed between the first and second source/drain regions.