Buried biasing wells in FETs (Field Effect Transistors)
AssigneeInternational Business Machines Corporation
InventorsHussein I. Hanafi, Edward J. Nowak
Life of this patent
Estimating the term…
Abstract
A method for fabricating a semiconductor structure. The semiconductor structure comprises first and second source/drain regions; a channel region disposed between the first and second source/drain regions; a buried well region in physical contact with the channel region; and a buried barrier region being disposed between the buried well region and the first source/drain region and being disposed between the buried well region and the second source/drain region, wherein the buried barrier region is adapted for preventing current leakage and dopant diffusion between the buried well region and the first source/drain region and between the buried well region and the second source/drain region.
Claims24
A method for forming a semiconductor structure, the method comprising the steps of:
- (a) providing a semiconductor substrate covered on top with a mandrel layer;
- (b) etching a trench through the mandrel layer and into the substrate;
- (c) forming a buried barrier region on a side wall of the trench, wherein the buried barrier region is in direct physical contact with both the substrate and the mandrel layer;
- (d) forming a buried well region and a channel region in the trench, wherein the channel region is on top of the buried well region;
- and
- (e) forming first and second source/drain regions,
- wherein the channel region is disposed between the first and second source/drain regions, and
- wherein the buried barrier region is disposed between the buried well region and the first source/drain region and is disposed between the buried well region and the second source/drain region.
A method for forming a semiconductor structure, the method comprising the steps of:
- (a) providing a semiconductor substrate covered on top with a mandrel layer;
- (b) etching a trench through the mandrel layer and into the substrate;
- (c) forming a buried barrier region on a side wall of the trench, wherein the buried barrier region is in direct physical contact with both the substrate and the mandrel layer;
- (d) depositing a semiconductor material in the trench so as to form an under-gate region such that the buried barrier region is completely buried in the under-gate region;
- (e) forming a gate spacer region on side walls of the trench;
- (f) doping via the trench a portion of the under-gate region which is surrounded by the buried barrier region, wherein the doped portion of the under-gate region comprises a buried well region, and wherein an undoped portion of the under-gate region on top of the buried well region comprises a channel region;
- (g) forming a gate dielectric layer on top of the channel region;
- (h) forming a gate region on top of the gate dielectric layer, wherein the gate region is electrically insulated from the channel region by the gate dielectric layer;
- and
- (i) forming first and second source/drain regions in the substrate,
- wherein the channel region is disposed between the first and second source/drain regions,
- wherein the buried barrier region is disposed between the buried well region and the first source/drain region and is disposed between the buried well region and the second source/drain region, and
- wherein the buried barrier region is adapted for preventing leakage current between the buried well region and the first source/drain region and between the buried well region and the second source/drain region.
A method for forming a semiconductor structure, the method comprising the steps of:
- (a) providing a silicon-on-insulator (SOI) substrate covered on top with a mandrel layer, wherein the SOI substrate includes (i) an upper semiconductor layer, (ii) a lower semiconductor layer, and (iii) an electrical insulator layer sandwiched between the upper and lower semiconductor layers;
- (b) etching a trench through the mandrel layer and into the SOI substrate such that the lower semiconductor layer is exposed to the atmosphere at a bottom wall of the trench;
- c) forming a buried barrier region on a side wall of the trench, wherein the buried barrier region is in direct physical contact with both the SOI substrate and the mandrel layer;
- (d) forming a buried well region and a channel region in the trench, wherein the channel region is on top of the buried well region;
- and
- (e) forming first and second source/drain regions,
- wherein the channel region is disposed between the first and second source/drain regions,
- wherein the buried barrier region is disposed between the buried well region and the first source/drain region and is disposed between the buried well region and the second source/drain region.
Dependencies are inferred from the claim text.