Split gate memory cell and method therefor
AssigneeFreescale Semiconductor, Inc.
InventorsErwin J. Prinz, Michael A. Sadd, Robert F. Steimle
Life of this patent
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Abstract
A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.
Claims12
A method for forming a split gate memory cell, comprising:
- forming a charge storage layer comprising nanocrystals over a substrate;
- forming a layer of control gate material over the charge storage layer, wherein the control gate material is formed of a semiconductor material that is doped to p type;
- patterning the layer of control gate material, wherein the patterning defines a first sidewall of a structure of the layer of control gate material;
- forming a layer of select gate material over the substrate and over the structure of the layer of control gate material after the patterning the layer of control gate material, wherein the select gate material is formed of semiconductor material that is doped to n type;
- and
- patterning the layer of select gate material and the structure of the layer of control gate material to define a stack sidewall, the stack sidewall including a first sidewall of a structure of the layer of select gate material and a second sidewall of the structure of the layer of control gate material, wherein the first sidewall of the structure of the layer of control gate material is an opposite sidewall to the second sidewall of the structure of the layer of control gate material.
Dependencies are inferred from the claim text.