High voltage deep trench capacitor
AssigneeFreescale Semiconductor, Inc.
InventorsRonghua Zhu, Vishnu Khemka, Amitava Bose, Todd C. Roggenbauer
Life of this patent
Estimating the term…
Abstract
A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).
Claims15
A method for fabricating a deep trench capacitor, comprising:
- providing a first semiconductor layer and a second semiconductor layer over at least part of the first semiconductor layer, where the second semiconductor layer is separated from the first semiconductor layer by an insulator layer;
- forming a first trench opening having substantially vertical sidewalls by selectively removing at least a portion of the second semiconductor layer in a first region to leave a remaining portion of the second semiconductor layer in a second region;
- forming a trench oxide region on at least one of the sidewalls of the first trench opening;
- forming a second trench opening that exposes a portion of the first semiconductor layer in the first region;
- forming a doped semiconductor layer in the second trench opening that is tied to the first semiconductor layer;
- and
- planarizing the doped semiconductor layer and the remaining portion of the second semiconductor layer;
- where the second semiconductor layer is doped with impurities to form a first capacitor plate, and where the doped semiconductor layer is doped with impurities to form a second capacitor plate that is separated from the first capacitor plate by the trench oxide region.
A method of forming a deep trench capacitor, comprising:
- providing a first substrate layer and a second substrate layer over the first substrate layer, where the second substrate layer is separated from the first substrate layer by a buried insulator layer;
- etching deep trenches through the second substrate layer and to at least the buried insulator layer;
- forming deep trench oxide regions on sidewalls of the deep trenches;
- exposing the first substrate layer within the deep trenches;
- forming a doped polysilicon layer over the deep trench oxide regions to fill the deep trenches, where the doped polysilicon layer contacts the exposed first substrate layer;
- and
- planarizing the doped polysilicon layer and the second substrate layer at least in part with a chemical mechanical polish step;
- where the second substrate layer is doped with impurities to form a first capacitor plate, and where the doped polysilicon layer is doped with impurities to form a second capacitor plate that is separated from the first capacitor plate by the deep trench oxide region.
Dependencies are inferred from the claim text.