US 7,730,366 B2 · Phase error determination method and digital phase-locked loop system

Abstract

In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.

Claims2

Dependent claims

A signal processing method having N phase clocks used in a digital phase-locked loop system, said method comprising the steps of:

inputting an asynchronous signal;
generating N phase clocks with a VCO that receives a reference clock as an input, the reference clock being derived from the asynchronous signal, the VCO output frequency is altered to be substantially coincident with the frequency of the asynchronous signal;
detecting a pulse length of the asynchronous signal by using the n-phase clocks to generate pulse-length data based on a timing relationship for changing points of the asynchronous signal determined with reference to the n-phase clocks;
and
thereby determining phase differences with the asynchronous signal and altering a voltage controlled oscillator based on the identified changing points for the asynchronous signal.

2 more elements

Dependencies are inferred from the claim text.

Phase error determination method and digital phase-locked loop system

Life of this patent

Phase error determination method and digital phase-locked loop system

Life of this patent

Abstract

Claims2