Method and apparatus for dynamic voltage and frequency scaling
AssigneeIntel Corporation
InventorsChunling Hu, Jack Liu
Life of this patent
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Abstract
A machine learning technique is used to improve dynamic prediction of processor utilization for multi-threaded user-level applications in a dynamic run-time environment based on processor utilization history. Processor supply voltage and processor clock frequency may be dynamically scaled based on the predicted processor utilization in order to reduce processor power consumption.
Claims18
An apparatus comprising:
- a run length encoding Markov model to store a phase transition history sequence and a predicted next power state for each of a plurality of power states based on predicted utilization of a processor by a multi-threaded application executing in a dynamic run-time environment;
- and
- a power manager to determine a next power state for the processor for a next time interval based upon detected utilization of the processor during a time interval, the next power state selected dependent on the stored phase transition history sequence for a current power state and on a run length encoding for a phase identifier.
A method comprising:
- based on predicted utilization of a processor by a multi-threaded application executing in a dynamic run-time environment, storing in a run length encoding Markhov model, a phase transition history sequence for each power state and a predicted next power state;
- and
- based upon detected utilization of the processor during a time interval, determining, by a power manager module, a next power state for the processor for a next time interval, the next power state selected dependent on the stored phase transition history sequence for a current power state and on a run length encoding for a phase identifier.
A non-transitory computer usable medium including a computer readable code stored thereon having associated information, wherein the information, when accessed, results in a machine performing:
- based on predicted utilization of a processor by a multi-threaded application executing in a dynamic run-time environment, storing, in a run length encoding Markhov model, a phase transition history sequence for each power state and a predicted next power state;
- and
- based upon detected utilization of the processor during a time interval, determining, by a power management module, a next power state for the processor for a next time interval, the next power state selected dependent on the stored phase transition history sequence for a current power state and on a run length encoding for a phase identifier.
Dependencies are inferred from the claim text.