Low power, high performance, heterogeneous, scalable processor architecture
Assignee3Plus1 Technology, Inc.
InventorsAmit Ramchandran, John Reid Hauser, Jr.
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Abstract
One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.
Claims36
A heterogeneous, scalable processor, said processor comprising:
- a first heterogeneous programmable integrated circuit sub-processor configured for 16, 24, 32 and 64-bit processing;
- and
- a second heterogeneous programmable integrated circuit sub-processor configured for 8, 4 and 1-bit processing,
- wherein at least one of the first and second sub-processors includes one or more macro-functional units (MFUs) corresponding to a programmable subset of one or more commonly occurring operations of target applications,
- wherein each of the MFUs include a local memory therein for local computation, and are configured for rearrangement of data values to and from the local memory, and
- wherein each of the first and second sub-processors can only execute one function or stream of data at a time, and include a built in control block dedicated to controlling and synchronizing an order of function execution.
A method for operating a heterogeneous, scalable processor, said method comprising:
- performing 16, 24, 32 and 64-bit processing by a first heterogeneous programmable integrated circuit sub-processor;
- performing 8, 4 and 1-bit processing by a second heterogeneous programmable integrated circuit sub-processor;
- providing in at least one of the first and second sub-processors, one or more macro-functional units (MFUs) corresponding to a programmable subset of one or more commonly occurring operations of target applications;
- including in each of the MFUs a local memory for local computation for rearranging of data values to and from the local memory;
- executing only one function or stream of data at a time with each of the first and second sub-processors;
- and
- controlling and synchronizing an order of function execution in each of the first and second sub-processors with a built in, dedicated control block.
Dependencies are inferred from the claim text.