Multiplier operable to perform a variety of operations
AssigneeAltera Corporation
InventorsJames L. Ball, James R. Lawson
Life of this patent
Estimating the term…
Abstract
Methods and apparatus are provided for implementing circuitry operable to perform barrel shifting, multiplication, and rotation operations in hard coded logic on a programmable chip. A hard coded multiplier is augmented using multiplexer circuitry, a logical operation, and a bypassable 2^N functional block. Based on control signals, the multiplexer circuitry can be used to select a rotation, multiplication, or barrel shifted output. Multiplexer control signals also provide sign information associated with operands passed to the multiplier. A single augmented multiplier can perform barrel shifting, rotation, or multiplication operations. Inputs of a multiplier can also be selectively grounded to allow the multiplier to perform logic operations.
Claims13
A circuit operable to perform multiplication, shifting, and rotation, the circuit comprising:
- a multiplier implemented using hard-logic on a programmable chip, the multiplier including a first multiplier input, a second multiplier input, and a multiplier output, wherein the first multiplier input provides a first operand and the second multiplier input provides a second operand;
- multiplexer circuitry connected to the multiplier, the multiplexer circuitry including a first multiplexer input, a second multiplexer input, a third multiplexer input, and a multiplexer output, the third multiplexer input a bitwise OR of the first multiplexer input and the second multiplexer input, wherein the first multiplexer input includes the most significant bits associated with the multiplier output and the second multiplexer input includes the least significant bits associated with the multiplier output.
A circuit operable to perform multiplication, shifting, and rotation, the circuit comprising:
- multiplier means on a programmable chip, the multiplier means including a first multiplier input, a second multiplier input, and a multiplier output, wherein the first multiplier input provides a first operand and the second multiplier input provides a second operand;
- multiplexer means connected to the multiplier means, the multiplexer means including a first multiplexer input, a second multiplexer input, a third multiplexer input, and a multiplexer output, the third multiplexer input a bitwise OR of the first multiplexer input and the second multiplexer input, wherein the first multiplexer input includes the most significant bits associated with the multiplier output and the second multiplexer input includes the least significant bits associated with the multiplier output.
Dependencies are inferred from the claim text.