# US 7,716,553 B2 · System and method for designing RS-based LDPC code decoder

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- Number: US 7,716,553 B2
- Document ID: US7716553B2
- Status: Granted
- Kind: B2
- Application number: 11/487,042
- Filed: 2006-07-13
- Published: 2007-02-08
- Granted: 2010-05-11
- Earliest claimed: 2005-07-13
- Assignees: Leanics Corporation
- Inventors: Sang-Min Kim; Keshab K. Parhi; Renfei Liu
- Web page: https://patentgrep.com/patent/US7716553B2

## CPC

- H03M 13/1151: {Algebraically constructed LDPC codes, e.g. LDPC codes derived from Euclidean geometries [EG-LDPC codes] (H03M13/116, H03M13/1174 take precedence)}
- H03M 13/1111: {Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms}
- H03M 13/1137: {Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A memory address generation method and circuit architecture for time-multiplexed RS-based LDPC code decoder is presented. The method is developed for non quasi-cyclic RS-based LDPC code decoder implementation. A circuit for the memory address generation method achieves low area. High throughput time-multiplexed RS-based LDPC code decoder design models and circuit architectures are presented. The decoder models are specifically developed for 10BASE-T (10-Gigabit Ethernet Transceiver Over Copper) system. These time-multiplexed architectures enable higher throughput with lower area.

## Claims

### Claim 1

A Reed-Solomon code based low-density parity check code decoder, comprising:
a check node unit (CNU) bank including a plurality of CNUs;
a variable node unit (VNU) including a plurality of VNUs;
a first memory address generator for CNU processing including a reference memory address block and an offset memory address block to generate a memory address from an exclusive-or of a reference memory address and an offset memory address;
a second memory address generator for VNU processing including a counter;
a memory unit addressed by a memory address generated by one of the first and second memory address generators;
a data transfer channel between the memory unit and the VNU bank, and
a data transfer channel between the memory unit and the CNU bank.

### Claim 2 (depends on 1)

The decoder of claim 1, further including at least one multiplexor to receive memory addresses from the first and second memory address generators and to select one of the addresses to address the memory unit.

### Claim 3

An integrated circuit to implement a Reed-Solomon (RS) code based low-density parity check code decoder, comprising:
a check node unit (CNU) bank including a plurality of CNUs;
a variable node unit (VNU) bank including a plurality of VNUs;
a first memory address generator for CNU processing including a reference memory address block and an offset memory address block to generate a memory address from an exclusive-or of a reference memory address and an offset memory address;
a second memory address generator for VNU processing including a counter;
a memory unit addressed by a memory address generated by one of the first and second memory address generators;
a data transfer channel between the memory unit and the VNU bank; and
a data transfer channel between said memory unit and said CNU bank.

### Claim 4 (depends on 3)

The integrated circuit of claim 3, further including at least one multiplexor to receive memory addresses from the first and second memory address generators and to select one of the addresses to address the memory unit.

### Claim 5

A decoder for decoding a low-density parity check (LDPC) code, comprising:
(a) a CNU bank comprising a plurality of check node units (GNU's),
(b) a VNU bank comprising a plurality of variable node units (VNU's),
(c) a sign and sum accumulation unit (SSAU) bank comprising a plurality of SSAU units,
(d) a first memory bank for storing extrinsic messages,
(e) a second memory bank for storing intrinsic messages,
(f) a first switch network transferring data from the said CNU bank to the said VNU bank,
(g) a second switch network transferring data from the said VNU bank to the said first memory bank and to the said sign and sum accumulation unit bank,
(h) check node units coupled to the first memory bank and to the SSAU unit bank, comprising:
i. at least one lookup table (LUT),
(i) variable node units coupled to the first switch network and the said second memory bank,
(j) sign and sum accumulation unit (SSAU), for accumulating sign and sum of the check node messages, coupled to the second switch network comprising:
i. one sign accumulation unit and one sum accumulation unit.

### Claim 6 (depends on 5)

The decoder of claim 5 which is pipelined by placing at least one register in an inter-connection path carrying data from one bank to another bank.

### Claim 7 (depends on 5)

The decoder of claim 5 where the first and second switch networks contain a plurality of demultiplexers.

### Claim 8 (depends on 5)

The decoder of claim 5 wherein the connecting path from the CNU bank to the first switch network contains at least two registers, and the paths from the VNU bank to the SSAU and to the first memory bank contain at least two registers.

### Claim 9 (depends on 5)

The decoder of claim 5 used for a Ethernet over copper application.

### Claim 10

An integrated circuit having a substrate and a decoder for low-density parity check code disposed on said substrate, said decoder comprising:
(a) a CNU bank comprising a plurality of check node units (CNU's),
(b) a VNU bank comprising a plurality of variable node units (VNU's),
(c) a sign and sum accumulation unit (SSAU) bank comprising a plurality of SSAU units,
(d) a first memory unit for storing extrinsic messages,
(e) a second memory unit for storing intrinsic messages,
(f) a first switch network transferring data from the said CNU bank to the said VNU bank, a second switch network transferring data from the said VNU bank to the said first memory bank and to the said sign and sum accumulation unit bank,
(g) check node units coupled to the first memory bank and to the SSAU unit bank, comprising:
i. at least one lookup table (LUT),
(h) variable node units coupled to the first switch network and the said second memory bank,
(i) sign and sum accumulation unit (SSAU), for accumulating sign and sum of the check node messages, coupled to the second switch network comprising:
i. one sign accumulation unit and one sum accumulation unit.

### Claim 11 (depends on 10)

The integrated circuit of claim 10 which is pipelined by placing at least one register in an interconnection path carrying data from one bank to another bank.

### Claim 12 (depends on 10)

The integrated circuit of claim 10 where the first and second switch networks contain a plurality of demultiplexers.

### Claim 13 (depends on 10)

The integrated circuit of claim 10 wherein the connecting path from the CNU bank to the first switch network contains at least two registers, and the paths from the VNU bank to the SSAU and to the first memory bank contain at least two registers.

### Claim 14 (depends on 10)

The integrated circuit of claim 10 used for a Ethernet over copper application.

### Claim 15

A decoder for decoding a low-density parity check (LDPC) code, comprising:
(a) a CNU bank comprising a plurality of check node units (CNU's),
(b) a VNU bank comprising a plurality of variable node units (VNU's),
(c) a first memory bank for storing extrinsic messages, coupled to the said CNU bank,
(d) a second memory bank, for storing intrinsic messages, whose output is coupled to the VNU bank,
(e) a first switch network, transferring data from the said first memory bank to the said VNU bank, comprising a plurality of demultiplexers,
(f) a second switch network, transferring data from the said VNU bank to the said first memory bank, comprising a plurality of demultiplexers,
(g) check node units coupled to the said first memory bank,
(h) variable node units coupled to the said first switch network and the said second memory bank.

### Claim 16 (depends on 15)

The decoder of claim 15 which is pipelined by placing at least one register in an inter-connection path carrying data from one bank to another bank.

### Claim 17 (depends on 15)

The decoder for claim 15 used for a Ethernet over copper application.

### Claim 18

An integrated circuit having a substrate and a decoder for a low-density parity check code disposed on said substrate, said decoder comprising:
(a) a CNU bank comprising a plurality of check node units (CNU's),
(b) a VNU bank comprising a plurality of variable node units (VNU's),
(c) a first memory bank for storing extrinsic messages, coupled to the said CNU bank,
(d) a second memory bank, for storing intrinsic messages, whose output is coupled to the VNU bank,
(e) a first switch network, transferring data from the said first memory bank to the said VNU bank, comprising a plurality of demultiplexers,
(f) a second switch network, transferring data from the said VNU bank to the said first memory bank, comprising a plurality of demultiplexers,
(g) check node units coupled to the first memory bank,
(h) variable node units coupled to the said first switch network and the said second memory bank.

### Claim 19 (depends on 18)

The integrated circuit of claim 18 which is pipelined by placing at least one register in an interconnection path carrying data from one bank to another bank.

### Claim 20 (depends on 18)

The integrated circuit for claim 18 used for a Ethernet over copper application.

### Claim 21

A decoder for decoding a low-density parity check (LDPC) code, comprising:
(a) a CNU bank comprising a plurality of check node units (CNU's),
(b) a VNU bank comprising a plurality of variable node units (VNU's),
(c) a first memory bank for storing extrinsic messages, coupled to the said VNU bank,
(d) a second memory bank, for storing intrinsic messages, whose output is coupled to the VNU bank,
(e) a first switch network, transferring data from the said first memory bank to the said GNU bank, comprising a plurality of demultiplexers,
(f) a second switch network, transferring data from the said CNU bank to the said first memory bank, comprising a plurality of demultiplexers,
(g) check node units coupled to the first switch network,
(h) variable node units coupled to the said first memory bank and the said second memory bank.

### Claim 22 (depends on 21)

The decoder of claim 21 which is pipelined by placing at least one register in an inter-connection path carrying data from one bank to another bank.

### Claim 23 (depends on 21)

The decoder for claim 21 used for a Ethernet over copper application.

### Claim 24

An integrated circuit having a substrate and a decoder for a low-density parity check code disposed on said substrate, said decoder comprising:
(a) a CNU bank comprising a plurality of check node units (CNU's),
(b) a VNU bank comprising a plurality of variable node units (VNUs),
(c) a first memory bank for storing extrinsic messages, coupled to the said VNU bank,
(d) a second memory bank, for storing intrinsic messages, whose output is coupled to the VNU bank,
(e) a first switch network, transferring data from the said first memory bank to the said CNU bank, comprising a plurality of demultiplexers,
(f) a second switch network, transferring data from the said CNU bank to the said first memory bank, comprising a plurality of demultiplexers,
(g) check node units coupled to the first switch network,
(h) variable node units coupled to the said first memory bank and the said second memory bank.

### Claim 25 (depends on 24)

The integrated circuit of claim 24 which is pipelined by placing at least one register in an interconnection path carrying data from one bank to another bank.

### Claim 26 (depends on 24)

The integrated circuit for claim 24 used for a Ethernet over copper application.