Series regulator with fold-back over current protection circuit

A series regulator with an over current protection circuit, wherein the series regulator receives an input voltage at an input terminal and generates an output voltage at an output terminal, the series regulator comprising:

• a first amplifier circuit, connected between the input terminal and ground, having an inverting input that receives a reference voltage, a non-inverting input, and an output terminal;
• a current limiting transistor comprising a first NMOS transistor having a source connected to the output terminal of the first amplifier circuit, a drain connected to the input terminal, and a gate;
• a current sense transistor comprising a first PMOS transistor having a source connected to the input terminal, and a gate connected to the output terminal of the first amplifier circuit, wherein the current sense transistor generates a sense current;
• an output transistor comprising a second PMOS transistor having a source connected to the input terminal, a drain connected to the output terminal, and a gate connected to the output terminal of the first amplifier circuit;
• an attenuator circuit comprising a voltage divider circuit having at least three series connected resistors, a first resistor being connected to the output terminal, a third resistor being connected to the ground, and a second resistor being connected between the first and third resistors, wherein a first voltage signal is generated at a node between the second and third resistors, and a second voltage signal being generated at a node between the first and second resistors, wherein the first voltage signal is provided to a non-inverting input terminal of the first amplifier circuit;
• a cascode device comprising a second NMOS transistor having a drain connected to a gate of the first NMOS transistor;
• a voltage-to-current converter comprising a third NMOS transistor having a drain connected to a source of the second NMOS transistor and a gate connected to the attenuator circuit and receiving the second voltage signal therefrom;
• a first current source connected between a source of the third NMOS transistor and the ground;
• a high ratio current mirror circuit comprising third and fourth PMOS transistors, wherein the third PMOS transistor has a source connected to a drain of the first PMOS transistor, and a drain connected to the drain of the third NMOS transistor, and wherein the fourth PMOS transistor has source connected to the source of the third PMOS transistor, a drain connected to the output terminal, and a gate connected to its drain and to a gate of the third PMOS transistor, and wherein the current mirror circuit receives the sense current from the current sense transistor and returns the sense current to the output terminal;
• a second current source connected between the input terminal and the drain of the second NMOS transistor;
• and
• a third current source connected between the source of the second NMOS transistor and the ground, wherein the current mirror circuit controls the gate voltage of the output transistor such that the output current generated at the output terminal is proportional to an output current of the voltage-to-current converter.