Macrocell and method for adding

A macrocell, comprising:

• an adder block comprising a plurality of bit-slice adders corresponding to a sequence of consecutive significance bit positions of input values, the bit-slice adders being adapted, depending on one of the input values or intermediate values depending thereon, and a carry of a first neighboring macrocell associated with lower-significance bit positions as processed by bit-slice adders corresponding to lower-significance bit positions during processing of the carry of the first neighboring macrocell through the adder block, to process the carry of the first neighboring macrocell and determine output values and to latch the one of the input values or the intermediate values depending thereon responsive to a first control signal;
• a bypass path;
• and
• a control unit being configured to receive the carry of the first neighboring macrocell in dual-rail coded form on two carry input lines, and to output a carry by generation within the adder block or by passage through the bypass path to a second neighboring macrocell associated with higher-significance bit positions in dual-rail coded form on two carry output lines, and to determine from data depending on the input values of the adder block whether the carry of the first neighboring macrocell may pass the bypass path to the second neighboring macrocell, and to enable the first control signal in a predetermined timing relative to a common clock signal common to the first neighboring macrocell and the macrocell, so that the carry of the first neighboring macrocell is accepted as an input for and then forwarded to the adder block during enablement of the first control signal.

A three-operands ALU for processing three input values, comprising:

• an ALU block comprising:
• a plurality of bit-slice ALUs corresponding to a sequence of consecutive significance bit positions of the three input values, each of the bit-slice ALUs comprising:
• a three bit format converter being adapted, depending on three input bits associated with a respective one of the significance bit positions, to calculate a half-adder output bit and an additional carry bit, the additional carry bit being input to a bit-slice ALU corresponding to next higher-significance bit positions of the three input values;
• and
• a 2 bits full adder, being adapted, depending on the format converter output bit or intermediate bits depending thereon, depending on an additional carry bit associated with a bit-slice ALU corresponding to the next lower-significance bit position of the three input values and depending on a carry of a first neighboring three-operands ALU associated with lower-significance bit position as processed by bit-slice ALUs corresponding to lower-significance bit positions of the ALU block, to process the carry of the first neighboring three-operands ALU and determine a three-operands ALU output bit and to latch the format converter output bit or the intermediate bits depending thereon responsive to a first control signal;
• the ALU block further comprising:
• a bypass path;
• and
• a control unit being configured to receive the carry of the first neighboring three-operands ALU in dual-rail coded form on two carry input lines, and to output the carry by generation within the ALU block or by passage through the bypass path to a second neighboring three-operands ALU associated with higher-significance bit positions in dual-rail coded form on two carry output lines and to determine from data depending on the three input values of the ALU block whether the carry of the first neighboring three-operands ALU may pass the bypass path to the second neighboring three-operands ALU, and to enable the first control signal in a predetermined timing relative to a common clock signal, common for the first neighboring three-operands ALU and the three-operands ALU, so that the carry of the first neighboring three-operands ALU is accepted as an input for and forwarded to the ALU block during enablement of the first control signal.

A method for adding using an adder block having a plurality of bit-slice adders corresponding to a sequence of consecutive significance bit positions of input values, comprising:

• receiving a carry associated with lower-significance bit positions in dual-rail coded form;
• preventing forwarding the carry associated with lower-significance bit positions depending on a validity associated with the carry associated with lower-significance bit positions;
• determining from data depending on the input values whether the carry associated with lower-significance bit positions may enable a bypass path;
• outputting a carry associated with lower-significance bit positions by generation within the adder block or by passage of the carry associated with lower-significance bit positions through the bypass path in dual-rail coded form;
• and
• signaling validity of the carry output depending on a dual-rail code of the carry output.