US 7,700,466 B2 · Tunneling effect transistor with self-aligned gate

Abstract

In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor.

Claims5

Dependent claims

A method of manufacturing a semiconductor structure comprising:

forming a mandrel on a semiconductor region in a semiconductor substrate;
forming an outer dummy spacer on sidewalls of said mandrel, wherein a portion of said semiconductor region is located outside said mandrel and said outer dummy spacer;
forming a first conductivity type region in said portion of said semiconductor region;
removing said mandrel to form a recessed region and forming a second conductivity type region underneath said recessed region;
and
removing said outer dummy spacer and forming a gate electrode comprising a gate dielectric and a gate conductor directly on said first conductivity type region and said second conductivity type region.

3 more elements

Dependencies are inferred from the claim text.

Tunneling effect transistor with self-aligned gate

Life of this patent

Tunneling effect transistor with self-aligned gate

Life of this patent

Abstract

Claims5