Multi-level cell resistance random access memory with metal oxides

A resistance random access memory structure, comprising:

• a first resistive memory member having a first metal oxide strip at a first position and a second metal oxide strip at a second position, the first position spaced apart from the second position;
• a second resistive memory member having a third metal oxide strip at a third position and a fourth metal oxide strip at a fourth position, the third position spaced apart from the fourth position;
• a first interconnect electrically coupling the first metal oxide strip of the first resistive memory member and the third metal oxide strip of the second resistive memory member;
• a second interconnect electrically coupling the second metal oxide strip of the first resistive memory member and the fourth metal oxide strip of the second resistive memory member;
• and
• an upper contact electrically contacting the second resistive memory member and a lower contact electrically contacting the first resistive memory member,
• the resistive memory members, the interconnects and the contacts being arranged to provide a current path that includes the lower contact, and divides to include first and second current branches that recombine to include the upper contact, the first current branch including the first metal oxide strip, the first interconnect, and the third metal oxide strip, and the second current branch including the second metal oxide strip, the second interconnect, and the fourth metal oxide strip.

A resistance random access memory structure, comprising:

• a first resistive memory member disposed in a first layer of the structure, the first resistive memory member having a first electrically conductive region and having a first metal oxide strip at a first position in the first layer and a second metal oxide strip at a second position in the first layer, the first position spaced apart from the second position within the first layer and the first electrically conductive region electrically connecting the first metal oxide strip to the second metal oxide strip;
• a second resistive memory member disposed in a second layer of the structure which is above the first layer of the structure, the second resistive memory member having a second electrically conductive region and having a third metal oxide strip at a third position in the second layer and a fourth metal oxide strip at a fourth position in the second layer, the third position spaced apart from the fourth position within the second layer and the second electrically conductive region electrically connecting the third metal oxide strip to the fourth metal oxide strip;
• a first interconnect electrically coupling the first metal oxide strip of the first resistive memory member and the third metal oxide strip of the second resistive memory member;
• and
• a second interconnect electrically coupling the second metal oxide strip of the first resistive memory member and the fourth metal oxide strip of the second resistive memory member.

A resistance random access memory structure, comprising:

• a two-terminal resistive memory device including:
• a first resistive memory member having a first metal oxide strip at a first position and a second metal oxide strip at a second position, the first position spaced apart from the second position;
• a second resistive memory member having a third metal oxide strip at a third position and a fourth metal oxide strip at a fourth position, the third position spaced apart from the fourth position;
• a first interconnect electrically coupling the first metal oxide strip of the first resistive memory member and the third metal oxide strip of the second resistive memory member;
• a second interconnect electrically coupling the second metal oxide strip of the first resistive memory member and the fourth metal oxide strip of the second resistive memory member;
• and
• a first terminal of the device electrically contacting the first resistive memory member between the first and second metal oxide strips and the second terminal of the device electrically contacting the second resistive memory member between the third and fourth metal oxide strips,
• the resistive memory members, the interconnects and the contacts in the device being arranged to provide a first current path that includes the first terminal of the device, the first metal oxide strip of the device, the first interconnect of the device, the third metal oxide strip of the device, and the second terminal of the device, and a second current path that includes the first terminal of the device, the second metal oxide strip of the device, the second interconnect of the device, the fourth metal oxide strip of the device, and the second terminal of the device;
• the memory structure further including:
• an access switch series-connected with the device;
• and
• a sense amplifier connected to sense a value stored in the device in dependence upon electrical resistance across the first arid second terminals of the device when the access switch is conducting.