Analog-to-digital converter having reduced number of activated comparators
AssigneeAgere Systems Inc.
InventorsErik Chmelar, Choshu Ito
Life of this patent
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Abstract
An ADC circuit includes multiple comparators and a controller coupled to the comparators. Each of the comparators is operative to generate an output indicative of a difference between a first signal representative of an input signal applied to the ADC circuit and a corresponding reference signal. The controller is operative to perform at least one of: (i) activating a subset of the comparators during a given sample period being; and (ii) controlling levels of the corresponding reference signals of the comparators as a function of a level of the input signal. A number of active comparators during the given sample period is no greater than one less than a number of regions into which the input signal is quantized.
Claims20
An analog-to-digital converter (ADC) circuit, comprising:
- a plurality of comparators, each of the comparators being operative to generate an output indicative of a difference between a first signal representative of an input signal applied to the ADC circuit and a corresponding reference signal;
- and
- a controller coupled to the plurality of comparators, the controller being operative to perform at least one of:
- (i) activating a subset of the plurality of comparators during a given sample period, wherein the subset of the plurality of comparators is directly dependent upon unencoded outputs of a least two of the plurality of comparators during a first set of one or more previous sample periods;
- and (ii) controlling levels of the corresponding reference signals of at least two of the plurality of comparators, wherein the levels of the corresponding reference signals are directly dependent upon the unencoded outputs of the at least two of the plurality of comparators during the first set of one or more previous sample periods.
A method for reducing power consumption in an analog-to-digital converter (ADC) circuit including a plurality of comparators, each of the comparators having a corresponding reference signal associated therewith, the method comprising the steps of:
- defining a plurality of regions into which an analog input signal applied to the ADC circuit is quantized;
- performing at least one of:
- activating a subset of the plurality of comparators during a given sample period, wherein the subset of the plurality of comparators is directly dependent upon unencoded outputs of at least two of the plurality of comparators during a first set of one or more previous sample periods;
- and controlling levels of the corresponding reference signals of at least two of the plurality of comparators, wherein the levels of the corresponding reference signals are directly dependent upon the unencoded outputs of the at least two of the plurality of comparators during the first set of one or more previous sample periods;
- and
- generating an output signal as a function of respective outputs of active comparators in the ADC circuit during the given sample period, the output signal for the given sample period being a digital representation of the analog input signal.
An electronic system, comprising:
- at least one integrated circuit including at least one analog-to-digital converter (ADC) circuit, the at least one ADC circuit comprising:
- a plurality of comparators, each of the comparators being operative to generate an output indicative of a difference between a first signal representative of an input signal applied to the ADC circuit and a corresponding reference signal;
- and
- a controller coupled to the plurality of comparators, the controller being operative to perform at least one of:
- (i) activating a subset of the plurality of comparators during a given sample period, wherein the subset of the plurality of comparators is directly dependent upon unencoded outputs of at least two of the plurality of comparators during a first set of one or more previous sample periods;
- and (ii) controlling levels of the corresponding reference signals of at least two of the plurality of comparators, wherein the levels of the corresponding reference signals are directly dependent upon the unencoded outputs of the at least two of the plurality of comparators during the first set of one or more previous sample periods.
Dependencies are inferred from the claim text.