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US 7,696,791 B2Granted
High-speed amplitude detector with a digital output
AssigneeIntel Corporation
InventorSami Hyvonen
Life of this patent
Estimating the term…
Abstract
An amplitude detection circuit using a sinusoidal input signal inputs to produce a digital output (a one or zero) is described. The circuit uses an input field effect transistor (FET) with a gate load coupled to a gate of the input FET. A drain load may be coupled to a drain of the input FET. A source load may be coupled to a source of the input FET. A controllable variable current generator provides a current to the source of the input FET, biasing the source of the input FET to a reference voltage. An input signal conductor may be coupled to the gate of the input FET. Other embodiments are described.
Claims12
An electrical circuit, comprising:
- a first input FET that partially controls output voltage signals responsive to an input voltage;
- a gate load coupled to a gate of the first input FET;
- a drain load coupled to a drain of the first input FET;
- a source load coupled to a source of the first input FET;
- a controllable variable current generator providing a current to the source of the first input FET, biasing the source of the first input FET to a reference voltage, wherein the controllable variable current generator comprises a source bias FET and an op amp, a source of the source bias FET and a positive input terminal of the op amp coupled to the source of the first input FET, a gate of the source bias FET coupled to the output terminal of the op amp, and a negative input terminal of the op amp coupled to a reference voltage conductor;
- a first input conductor coupled to the gate of the first input FET and an input voltage signal including a variable input signal applied to the first input conductor;
- and
- a gate bias voltage source coupled to the gate load wherein the gate bias voltage source comprises a gate bias FET, a bias current generator, and a bias resistor, and the gate load comprises a first input gate resistor, the bias current generator providing a current to a drain of the gate bias FET with the drain of the gate bias FET coupled to a gate of the gate bias FET and a first terminal of the first input gate resistor, a source of the gate bias FET coupled to the bias resistor, and a second terminal of the first input gate resistor coupled to a gate of the first input FET.
5 more elements
An electrical circuit, comprising:
- a first input FET coupled to a second input FET forming a differential pair amplifier, the source of the first input FET coupled to a source of the second input FET, and the drain of the first input FET coupled to a drain of the second input FET.
- a gate load coupled to a gate of the first input FET;
- a drain load coupled to a drain of the first input FET, wherein the drain load comprises a drain capacitor coupled to the drain of the first input FET, wherein the drain load comprises a second load FET and a third load FET connected in series, a source of the second load FET coupled to the drain of the first input FET, a drain of the second load FET coupled to a source of the third load FET, and an output conductor coupled to the drain of the first input FET;
- a source load coupled to a source of the first input FET;
- a controllable variable current generator to provide a current to the source of the first input FET, biasing the source of the first input FET to a reference voltage;
- a first input conductor coupled to the gate of the first input FET and a input voltage signal including a variable input signal applied to the first input conductor;
- a second input conductor coupled to the gate of the second input FET, and a second input voltage signal applied to the second input conductor, the second input voltage including an inverted input signal of the first input voltage signal.
4 more elements
An electrical circuit, comprising:
- a first input FET coupled to a second input FET forming a differential pair amplifier, the source of the first input FET coupled to a source of the second input FET, and the drain of the first input FET coupled to a drain of the second input FET.
- a gate load coupled to a gate of the first input FET;
- a drain load coupled to a drain of the first input FET, wherein the drain load comprises a drain capacitor coupled to the drain of the first input FET, wherein the drain load comprises a first load FET, a second load FET, and a third load FET connected in series, a source of the first load FET coupled to the drain of the first input FET, a source of the second load FET coupled to a drain of the first load FET, and a drain of the second load FET coupled to a source of the third load FET, and an output conductor coupled to the drain of the first load FET;
- a source load coupled to a source of the first input FET;
- a controllable variable current generator to provide a current to the source of the first input FET, biasing the source of the first input FET to a reference voltage;
- a first input conductor coupled to the gate of the first input FET and a input voltage signal including a variable input signal applied to the first input conductor;
- a second input conductor coupled to the gate of the second input FET, and a second input voltage signal applied to the second input conductor, the second input voltage including an inverted input signal of the first input voltage signal.
4 more elements
Dependencies are inferred from the claim text.