Non-volatile multilevel memory cell programming

A method for programming a multilevel non-volatile memory cell, comprising:

• applying programming pulses to a word line associated with a multilevel memory cell to increase a threshold voltage (Vt) of the cell to a verify voltage (VFY) level corresponding to a particular program state among a number of program states, and applying an inhibit voltage to a bit line coupled to the cell in response to the Vt reaching the VFY level;
• changing a bias voltage applied to the bit line from a first value to a second value in response to the Vt reaching a pre-verify voltage (PVFY) level of a number of PVFY levels within a first number of programming pulses, wherein the PVFY levels are less than the VFY level, and wherein the first and second values are less than the inhibit voltage;
• adjusting the PVFY level from a first PVFY level associated with a first programming pulse to an uppermost PVFY level associated with a subsequent programming pulse over the first number of programming pulses;
• and
• if the Vt is less than the uppermost PVFY after the first number of programming pulses, changing the bias voltage applied to the bit line from the first value to a third value in response to the Vt reaching the uppermost PVFY level within a second number of programming pulses subsequent to the first number of programming pulses.

A memory device, comprising:

• an array of multilevel memory cells arranged in rows and columns such that the rows are coupled by word lines and the columns are coupled by bit lines, each memory cell having a threshold voltage (Vt);
• and
• control circuitry that controls programming of the array, the control circuitry configured to:
• control generation of programming pulses to increase the Vt of a number of memory cells until the memory cells are programmed to a particular state;
• and
• selectively control application of a selective slow programming convergence (SSPC) voltage to bit lines in response to the Vt of a memory cell coupled thereto reaching a modulated pre-verify voltage (PVFY) level, the modulated PVFY level being less than a verify voltage (VFY) level at which the number of memory cells are considered to be programmed;
• control application of an inhibit voltage to bit lines in response to the Vt of memory cells coupled thereto reaching the VFY level;
• and
• control modulation of the SSPC voltage.

A flash memory device, comprising:

• a NAND array of multilevel memory cells arranged in rows and columns such that the rows are coupled by word lines and the columns are coupled by bit lines, each memory cell having a threshold voltage (Vt);
• and
• control circuitry that controls programming of the NAND array, the control circuitry configured to:
• control generation of programming pulses to increase the Vt of a number of memory cells until each of the number of memory cells are programmed to a particular state;
• and
• selectively control application of a selective slow programming convergence (SSPC) voltage to bit lines in response to the Vt of a memory cell coupled thereto reaching a modulated pre-verify voltage (PVFY), the modulated PVFY being less than a verify voltage (VFY) at which the number of memory cells are considered to be programmed;
• control application of an inhibit voltage to bit lines in response to the Vt of memory cells coupled thereto reaching the VFY;
• and
• control modulation of the SSPC voltage, including
• maintaining the SSPC voltage at a first value over a number of incrementally stepped programming pulses;
• and
• decreasing the SSPC voltage on a pulse by pulse basis over a number of subsequent programming pulses at an uppermost programming pulse voltage.