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US 7,692,459 B2Granted
High resolution delay adjustor
AssigneeRealtek Semiconductor Corp.
InventorChao-Cheng Lee
Life of this patent
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Abstract
A delay adjustor for adjusting the delay time of a signal, the adjustor comprising: a first capacitance unit and a variable capacitance unit serially coupled to the first capacitor wherein the capacitance of the variable capacitance unit is adjusted according to a first control signal and the variable capacitance unit comprises a plurality of second capacitors and at least a first switch coupled to the at least one capacitor of the second capacitors.
Claims17
A delay adjustor for adjusting the delay time of a signal, comprising:
- a first capacitance unit;
- and
- a variable capacitance unit coupled in series to the first capacitance unit;
- wherein the capacitance of the variable capacitance unit is at least two times larger than the capacitance of the first capacitance unit and adjusted according to a first control signal, the first control signal is used to adjust the delay time of the signal, and the variable capacitance unit comprises a plurality of first capacitors and at least one first switch coupled to at least one of the first capacitors;
- and
- wherein the delay adjustor is coupled to an analog-to-digital converter and the analog-to- digital converter is a time-interleaved analog-to-digital converter.
3 more elements
Dependencies are inferred from the claim text.