Double diamond clock and power distribution
OwnerRobert P. Masleid, Scott Pitkethlyinventors
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Abstract
Systems and methods of double diamond clock and power distribution. In accordance with a first embodiment of the present invention, an integrated circuit comprises a first metallization layer. that is substantially a power plane and a second metallization layer disposed immediately adjacent to the first metallization layer. The first metallization layer and the second metallization layer are separated by an inter-plane distance. A signal trace on the first metallization layer is separated from the power plane by about three times the inter-plane distance.
Claims21
An integrated circuit comprising:
- a first metallization layer that is substantially a power plane;
- a second metallization layer;
- wherein said first metallization layer and said second metallization layer are separated by an inter-plane distance;
- and
- a signal trace on said first metallization layer separated from said power plane by about three times said inter-plane distance.
An integrated circuit comprising:
- a first substantially continuous metal plane disposed in a first metallization layer for conducting first power to elements of said integrated circuit;
- a second substantially continuous metal plane disposed in a second metallization layer for conducting second power to elements of said integrated circuit;
- wherein said first and second metallization layers are vertically adjacent;
- wherein said first and second substantially continuous metal planes comprise stripes that are substantially non-parallel to an edge of said integrated circuit;
- and
- wherein said first substantially continuous metal plane comprises a signal trace that is electrically isolated from said first power.
An integrated circuit comprising:
- a first metallization layer wherein the majority of metallization of said first metallization layer is electrically continuous at a first power potential;
- a second metallization layer wherein the majority of metallization of said second metallization layer is electrically continuous at a second power potential;
- a third metallization layer wherein the majority of metallization of said third metallization layer comprises a plurality of signal traces, wherein a majority of said signal traces are electrically isolated from one another;
- wherein said first metallization layer and said second metallization layer comprise stripes that are substantially non-parallel to an edge of said integrated circuit;
- wherein said stripes are at least 2 times the plan view width of said signal traces;
- and
- wherein said first metallization layer comprises a wiring trace that is eclectically isolated from said first power potential.
Dependencies are inferred from the claim text.