Programmable via modeling
AssigneeeASIC Corporation
InventorsJonathan Park, Yit Ping Kok, Soon Chieh Lim, Yin Hao Liew, Wai Leng Chek
Life of this patent
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Abstract
A method for verifying library components and designs on a via customizable ASIC, which may include the process of adding capacitors to model possible via sites of a model of an un-customized portion of or a whole ASIC, and replacing the capacitors with resistors to model where custom vias have been placed on the ASIC to implement a desired component or design. Views of this model may then be generated to verify the functionality of the component or design, and component models for timing, function and via customization may then be generated for the component library.
Claims8
A method of modeling designs customized in via-customizable integrated circuits, comprising:
- automatically creating a set of legal via sites by determining all intersections of user configurable metals adjacent to a via programmable layer and performing design rule checks to determine the legality of each via site;
- placing a model of an unselected via at a via sites in said set of legal via sites in a customizable integrated circuit;
- and
- replacing each model of an unselected via with a model of a selected via at customizable via sites to be utilized in a design to customize the customizable integrated circuit.
Dependencies are inferred from the claim text.