Identifying and improving robust designs using statistical timing analysis

A computer-readable medium embodying instructions that when executed by a processor would provide a tool set for generating circuits in a design flow for an implementation process, the tool set comprising:

• means for receiving library data for a design including timing models;
• means for defining a robust circuit based on at least one of worst negative slack and total negative slack as well as at least one of endpoint slack distribution and number of timing constraint violations;
• and
• means for using statistical timing analysis to drive logic changes that generate improved robust circuits in the design,
• wherein the statistical timing analysis models a statistical delay distribution on an arc of the design in static timing analysis, and
• wherein the statistical delay distribution on the arc includes:
• using a static timing delay associated with the arc in statistical timing analysis as a mean;
• and
• using a specified percentage of the mean as the standard deviation,
• wherein the specified percentage is obtained from one of an estimate of the clock budget for variations and from an estimate of delay variations on a gate.