Register retiming technique
AssigneeAltera Corporation
InventorsBabette van Antwerpen, Michael D. Hutton, Gregg Baeckler, Richard Yuan
Life of this patent
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Abstract
An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.
Claims20
A method for designing logic circuitry implemented by a programmable logic device, the method comprising:
- providing a design file incorporating the logic design circuitry in computer readable format;
- and with a computer aided design system;
- generating from the design file a retiming graph for each of a plurality of clock domains associated with the logic design circuitry;
- applying constraints to the retiming graph to determine which registers of the retiming graph are capable of being moved forward or backward across a combinational logic element of the logic design circuitry;
- and
- retiming by using the computer aided design system, the logic design circuitry by moving compatible registers on the retiming graph backward or forward across the combinational logic elements until the difference between gate-to-gate delays for the logic design is minimized.
A method for designing logic circuitry implemented by a programmable logic device, the method comprising:
- providing a design file incorporating the logic design circuitry in computer readable format;
- and with an electronic design automation system;
- generating from the design file a retiming graph for each of a plurality of clock domains associated with the logic design circuitry;
- applying constraints to the retiming graph to determine which registers of the retiming graph are compatible and are capable of being moved forward or backward across a combinational logic element of the logic design circuitry;
- and
- retiming by using the electronic design automation system, the logic design circuitry by moving compatible registers on the retiming graph backward or forward across the combinational logic elements until the difference between gate-to-gate delays for the logic design is minimized,
- wherein the registers are compatible if they have the same clock-enable.
A method for designing logic circuitry implemented by a programmable logic device, the method comprising:
- providing a design file incorporating the logic design circuitry in computer readable format;
- and with a computer;
- generating from the design file a retiming graph for each of a plurality of clock domains associated with the logic design circuitry;
- applying constraints to the retiming graph to determine which registers of the retiming graph are compatible and are capable of being moved forward or backward across a combinational logic element of the logic design circuitry;
- and
- retiming by using the computer, the logic design circuitry by moving compatible registers on the retiming graph backward or forward across the combinational logic elements until the difference between gate-to-gate delays for the logic design is minimized,
- wherein the registers are compatible if they have they have the same asynchronous load.
Dependencies are inferred from the claim text.