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US 7,689,953 B1Granted
Method and apparatus for determining cell-based timing elements from a transistor-level design
AssigneeGlobalfoundries Inc.
InventorsDavid M. Newmark, Mahesh S. Sharma
Life of this patent
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Abstract
The present invention provides a method and apparatus for determining cell-based timing elements based on a transistor-level circuit design. The method may include accessing information indicative of a transistor-level circuit design determining at least one component of at least one cell based on the information indicative of the transistor-level circuit design, and determining at least one time delay associated with the transistor-level circuit design based on said at least one component of at least one cell.
Claims19
A method, comprising:
- accessing, by a processing unit, information indicative of a transistor-level circuit design that characterizes a plurality of transistors in a circuit, connectivity between the transistors, and transistor-level parasitics;
- generating, in the processing unit, a cell-level circuit design based on the transistor-level circuit design, the cell-level circuit design comprising a plurality of cells, each cell being characterized by the information indicative of the transistor-level circuit design prior to initiating a static timing analysis, wherein generating the cell-level circuit design comprises determining at least one component of at least one of a channel-connected region or a channel-connected region group, wherein determining said at least one component of at least one of a channel-connected region and a channel-connected region group comprises folding together gates that match within a selected tolerance or range;
- and
- applying, in the processing unit, the static timing analysis to the cell-level circuit design to determine at least one time delay associated with the transistor-level circuit design.
1 more element
An apparatus, comprising:
- means for accessing information indicative of a transistor-level circuit design that characterizes a plurality of transistors in a circuit, connectivity between the transistors, and transistor-level parasitics;
- means for generating a cell-level circuit design based on the transistor-level circuit design, the cell-level circuit design comprising a plurality of cells, each cell being characterized by the information indicative of the transistor-level circuit design prior to initiating a static timing analysis, wherein generating the cell-level circuit design comprises determining at least one component of at least one of a channel-connected region or a channel-connected region group, wherein determining said at least one component of at least one of a channel-connected region and a channel-connected region group comprises folding together gates that match within a selected tolerance or range;
- and
- means for applying the static timing analysis to the cell-level circuit design to determine at least one time delay associated with the transistor-level circuit design.
1 more element
An apparatus, comprising:
- a processing unit configured to:
- access information indicative of a transistor-level circuit design that characterizes a plurality of transistors in a circuit, connectivity between the transistors, and transistor-level parasitics;
- generate a cell-level circuit design based on the transistor-level circuit design, the cell-level circuit design comprising a plurality of cells, each cell being characterized by the information indicative of the transistor-level circuit design, wherein generating the cell-level circuit design comprises determining at least one component of at least one of a channel-connected region or a channel-connected region group, wherein determining said at least one component of at least one of a channel-connected region and a channel-connected region group comprises folding together gates that match within a selected tolerance or range;
- and
- apply the static timing analysis to the cell-level circuit design to determine at least one time delay associated with the transistor-level circuit design based on said at least one component of at least one cell.
2 more elements
Dependencies are inferred from the claim text.