US 7,689,946 B2 · High-performance FET device layout

Abstract

A fast FET and a method and system for designing the fast FET. The method includes: selecting a reference design for a field effect transistor, the field effect transistor including a source, a drain, a channel between the source and drain, a gate electrode over the channel, at least one source contact to the source and at least one contact to the drain, the at least one source contact spaced a first distance from the gate electrode and the at least one drain contact spaced a second distance from the gate electrode; and adjusting the first distance and the second distance to maximize a performance parameter of the field effect transistor to create a fast design for the field effect transistor.

Claims32

Dependent claims

A method comprising:

selecting a reference design for a field effect transistor, said field effect transistor including a source, a drain, a channel between said source and drain, a gate electrode over said channel, one or more source contacts to said source and one or more drain contacts to said drain, each of said one or more source contacts spaced a first distance from said gate electrode and each of said one or more drain contacts spaced a second distance from said gate electrode;
adjusting said first distance and said second distance to maximize a performance parameter of said field effect transistor to create a fast design for said field effect transistor;
displaying said fast design on a display device of a computer system;
and
wherein said performance parameter is a power cut-off frequency of said field effect transistor or a current cut-off frequency of said field effect transistor.

2 more elements

Dependencies are inferred from the claim text.

High-performance FET device layout

Life of this patent

High-performance FET device layout

Life of this patent

Abstract

Claims32