US 7,689,942 B2 · Simultaneous power and timing optimization in integrated circuits by performing discrete actions on circuit components

Abstract

A graph-based iterative method is provided for selecting component modifications in an integrated circuit design that reduce the power consumption to a minimum while still meeting timing constraints. Channel-connected components are represented as nodes in a timing graph and edges in the timing graph represent directed paths. From the timing graph, a move graph is constructed containing a plurality of move nodes. Each move node represents a change to one of the components in one of the timing graph nodes. A given timing graph node can result in a plurality of move nodes. Move nodes can be merged into group nodes, and both the move nodes and group nodes are assigned a weight based on the change in power and timing effects of the associated components changes. These weights are used to select move nodes or group nodes. In general, a set of move or group nodes is selected representing the maximum cumulative weight and the components changes associated with the nodes in the set are performed on the integrated circuit design. Moves that cause timing violations are reversed. The node weights are updated following components changes and the selection of node sets is repeated iteratively until the power consumption converges to a minimum.

Claims19

Dependent claims

A method for optimizing an integrated circuit design, the method comprising:

establishing an acyclic timing graph comprising a plurality of nodes and a plurality of directed edges, each node corresponding to a set of channel-connected components in an integrated circuit design and each directed edge corresponding to a path between a given pair of nodes;
converting the timing graph to a move graph comprising a plurality of move nodes and the plurality of directed edges by converting each timing graph node to a corresponding move node and maintaining the directed edges between given pairs of timing graph nodes between the corresponding move nodes, each move node corresponding to a single design change in at least a portion of one of the channel-connected components in the corresponding timing graph node, the single design change affecting power consumption of the integrated circuit design;
using the move graph to identify modifications to components in the integrated circuit design that reduce power consumption in the integrated circuit design without creating a timing violation;
and
modifying the integrated circuit design in accordance with the identified modifications.

2 more elements

A computer-readable medium containing a computer-readable code that when read by a computer causes the computer to perform a method for optimizing an integrated circuit design, the method comprising:

establishing an acyclic timing graph comprising a plurality of nodes and a plurality of directed edges, each node corresponding to a set of channel-connected components in an integrated circuit design and each directed edge corresponding to a path between a given pair of nodes;
converting the timing graph to a move graph comprising a plurality of move nodes and the plurality of directed edges by converting each timing graph node to a corresponding move node and maintaining the directed edges between given pairs of timing graph nodes between the corresponding move nodes, each move node corresponding to a single design change in at least a portion of one of the channel-connected components in the corresponding timing graph node, the single design change affecting power consumption of the integrated circuit design;
using the move graph to identify modifications to components in the integrated circuit design that reduce power consumption in the integrated circuit design without creating a timing violation;
and
modifying the integrated circuit design in accordance with the identified modifications.

2 more elements

Dependencies are inferred from the claim text.

Simultaneous power and timing optimization in integrated circuits by performing discrete actions on circuit components

Life of this patent

Simultaneous power and timing optimization in integrated circuits by performing discrete actions on circuit components

Life of this patent

Abstract

Claims19