US 7,689,941 B1 · Write margin calculation tool for dual-port random-access-memory circuitry

Abstract

Systems and methods are provided for computing write margins for dual-port memory. A design for a dual-port memory array cell is generated using a circuit design tool. A user modifies the design of the dual-port memory array cell to incorporate two voltage sources. The voltage sources are used to represent differential noise on the memory cell. A write margin calculation tool uses a circuit simulation tool to perform transient simulations of write-during-read operations on the modified dual-port memory array cell. During the transient simulations, the voltage level on the voltages sources is systematically varied. The write margin for the dual-port memory is determined by analyzing the results of the transient simulations for each of the voltage levels used for the voltage sources.

Claims20

Dependent claims

A method for computing, with computing equipment, a write margin for a dual-port memory array cell comprising:

with computing equipment, modifying the dual-port memory array cell to include a differential noise source;
with computing equipment, systematically varying a voltage setting for the differential noise source while performing write operation transient simulations for the modified dual-port memory array cell;
and
using results from the write operation transient simulations to determine the write margin for the dual-port memory array cell.

1 more element

Software on a computer-readable storage medium for computing a write margin for a dual-port memory array cell, wherein a user modifies the dual-port memory array cell to include a differential noise source to facilitate computation of the write margin, the software comprising:

code on the computer-readable storage medium for performing write operation transient simulations for the modified dual-port memory array cell while a voltage setting for the differential noise source is systematically varied;
and
code on the computer-readable storage medium for analyzing results from the write operation transient simulations to determine the write margin for the dual-port memory array cell.

Computing equipment for computing a write margin for a dual-port memory array cell, comprising:

a circuit design tool with which a user modifies the dual-port memory array cell to include a differential noise source to facilitate computation of the write margin;
a circuit simulation tool that performs write operation transient simulations for the modified dual-port memory array cell while a voltage setting for the differential noise source is systematically varied;
and
a write margin calculation tool that analyzes results from the write operation transient simulations to determine the write margin for the dual-port memory array cell.

1 more element

Dependencies are inferred from the claim text.

Write margin calculation tool for dual-port random-access-memory circuitry

Life of this patent

Write margin calculation tool for dual-port random-access-memory circuitry

Life of this patent

Abstract

Claims20