US 7,689,897 B2 · Method and device for high speed testing of an integrated circuit

Abstract

An integrated circuit and a method for testing an integrated circuit. The method includes providing a first high frequency clock signal sequence to a first group of components of an integrated circuit during a test sequence; characterized by receiving, by a first memory circuit within the integrated circuit, at a low reception rate, a first high frequency signal pattern information and a first low frequency signal pattern information; generating the first high frequency clock signal sequence in response to a first high frequency clock signal and in response to the first high frequency signal pattern information; wherein the first high frequency signal pattern information is being retrieved at a first high retrieval rate from the first memory circuit; and generating a first low frequency clock signal sequence in response a first low frequency clock signal and in response to the first low frequency signal pattern information; wherein the first high frequency signal pattern information is being retrieved at a low retrieval rate from the first memory circuit.

Claims26

Dependent claims

A method for testing an integrated circuit, the method comprises:

providing a first high frequency clock signal by a first high frequency clock source of the integrated circuit;
receiving, by a first memory circuit within the integrated circuit, at a low reception rate, a first high frequency signal pattern information and a first low frequency signal pattern information;
generating the first high frequency clock signal sequence in response to a first high frequency clock signal and in response to the first high frequency signal pattern information, wherein the first high frequency signal pattern information is being retrieved at a first high retrieval rate from the first memory circuit;
providing the first high frequency clock signal sequence to a first group of components of an integrated circuit during a test sequence;
and
generating a first low frequency clock signal sequence in response a first low frequency clock signal and in response to the first low frequency signal pattern information, wherein the first low frequency signal pattern information is being retrieved at a low retrieval rate from the first memory circuit.

3 more elements

An integrated circuit that comprises:

a first group of components;
a first high frequency clock generator for generating a first high frequency clock signal;
a first memory circuit, adapted to receive at a low reception rate, a first high frequency signal pattern information and a first low frequency signal pattern information, wherein the first high frequency signal pattern information and the first low frequency signal pattern information are being provided from an external test device;
a first clock signal sequence circuit adapted to generate a first high frequency clock signal sequence in response to the first high frequency signal pattern information and in response to the first high frequency clock signal, wherein the first high frequency signal pattern information is being retrieved at a first high retrieval rate from the first memory circuit and provided to the first group of components;
and
wherein the first clock signal sequence circuit is further adapted to generate a first low frequency signal sequence in response to the first low frequency signal pattern information and in response to a first low frequency clock signal;
wherein the first low frequency signal pattern information is being retrieved at a low retrieval rate from the first memory circuit and provided to the first group of components.

4 more elements

Dependencies are inferred from the claim text.

Method and device for high speed testing of an integrated circuit

Life of this patent

Method and device for high speed testing of an integrated circuit

Life of this patent

Abstract

Claims26