System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation

An information handling system comprising:

• one or more processors;
• a memory accessible by the processors;
• one or more nonvolatile storage devices accessible by the processors;
• and
• a set of instructions stored in the memory, wherein one or more of the processors executes the set of instructions in order to perform actions of:
• selecting a first lwarx instruction;
• pseudo-randomly selecting a first pseudo-random address for the first lwarx instruction;
• including the first lwarx instruction with the first pseudo-random address into the test pattern;
• reserving the first pseudo-random address for a first stwcx instruction that is paired to the first lwarx instruction;
• selecting the first stwcx instruction;
• including the first stwcx instruction with the first pseudo-random address into the test pattern, wherein a first conflicting instruction does not reside between the first lwarx instruction and the first stwcx instruction in the test pattern.

A computer program product stored on a computer operable media, the computer operable media containing instructions for execution by a computer, which, when executed by the computer, cause the computer to implement a method of processing test patterns, the method comprising:

• selecting a first lwarx instruction;
• pseudo-randomly selecting a first pseudo-random address for the first lwarx instruction;
• including the first lwarx instruction with the first pseudo-random address into the test pattern;
• reserving the first pseudo-random address for a first stwcx instruction that is paired to the first lwarx instruction;
• selecting the first stwcx instruction;
• including the first stwcx instruction with the first pseudo-random address into the test pattern , wherein a first conflicting instruction does not reside between the first lwarx instruction and the first stwcx instruction in the test pattern.