Integrated circuit and method for identifying propagation time errors in integrated circuits
AssigneeInfineon Technologies AG
InventorsMartin Kaibel, Olivier Barondeau
Life of this patent
Estimating the term…
Abstract
An integrated circuit is disclosed. In one embodiment, for each clock domain there is at least one clock driver which is situated in the integrated circuit and which drives circuits situated in the clock domain. Each clock driver in the clock domain contains a clock input and an enable input, and its output outputs the clock received at the clock input if an enable signal is applied to the enable input. The clock driver receives a clock derived from the signal at the functional clock input, and the enable signal is connected in line with the values stored in the signal sequence registers if there is a signal change at the scan clock input when the scan chain shift mode has been switched off.
Claims17
A method for identifying propagation time errors in integrated circuits comprising:
- defining an integrated circuit to include a multiplicity of scan cells, a functional clock input, a scan clock input and a multiplicity of clock domains, wherein the scan cells are connected as shift registers in a scan chain shift mode and each clock domain is operated by a dedicated clock driver situated in the integrated circuit;
- switching the scan chain shift mode on;
- shifting data into the scan cells by using signal changes at the scan clock input;
- applying clock signals to the functional clock input;
- programming signal sequence registers;
- switching the scan chain shift mode off;
- generating from the clock on the functional clock input, a multiplicity of clock signals in at least one clock domain according to values stored in the signal sequence registers;
- checking if propagation time errors have occurred in the clock domain operated;
- and wherein the generation of the clock signals is initiated by a signal change at the scan clock input.
An integrated circuit, comprising:
- a functional clock input;
- a scan clock input;
- a multiplicity of clock domains;
- in the clock domains a multiplicity of scan cells which are connected as shift registers in a scan chain shift mode and receive the clock from the scan clock input;
- for each clock domain at least one clock driver which is situated in the integrated circuit and which drives circuits situated in the clock domain;
- each clock driver in the clock domain contains a clock input and an enable input;
- and its output outputs the clock received at the clock input if an enable signal is applied to the enable input;
- and
- wherein the clock driver receives a clock derived from the signal at the functional clock input;
- and the enable signal is connected according to values stored in signal sequence registers if there is a signal change at the scan clock input after the scan chain shift mode has been switched off.
An integrated circuit, comprising:
- a scan clock input;
- a PLL having at least one clock output;
- a multiplicity of flipflops which respectively receive a clock signal and which are connected as shift registers in a scan chain shift mode;
- a multiplexer which drives the clock inputs of the flipflops;
- and
- switches the output of the PLL to the clock inputs of the flipflops in a functional mode;
- switches the signal at the scan clock input to the clock inputs of the flipflops in the scan chain shift mode;
- and switches a selection of pulses produced by the PLL to the clock inputs of the flipflops in a propagation time test;
- and
- wherein the multiplexer is in a form such that a path of the output signal to the flipflops is a same length both in the propagation time test and in the functional mode.
Dependencies are inferred from the claim text.