Multicore chip test
AssigneeAdvanced Micro Devices, Inc.
InventorMarkus Seuring
Life of this patent
Estimating the term…
Abstract
An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture. In particular, the provided approach enables the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test.
Claims18
An integrated circuit chip, comprising:
- a test input configured to receive test data;
- an expectation input for receiving expected result data;
- at least two circuitry cores, each core having a core test input and a core test output, each core being configured to receive test data from the test input at its core test input, to generate test result data according to the received test data, and further configured to provide the generated test result data at its core test output;
- comparator circuitry configured to compare for each core the test result data from the core test outputs and the received expected result data to detect for each core whether or not there is a mismatch between the test result data and the received expected result data;
- a mask logic unit which is configured to receive the received expected result data from the expectation input and to generate mask data from the expected result data by analyzing whether the values of expected mask data remain stable during a whole clock cycle, wherein the comparator circuitry is further arranged to receive mask data indicating for each of the circuitry cores whether or not the comparison of the test result data with the received expected result data is to be masked;
- and
- a memory configured to store for each core a mismatch indication.
A method for an integrated circuit chip for testing the circuitry of at least two circuitry cores included in the integrated circuit chip, the method comprising:
- receiving test data at a test input of the integrated circuit chip and expected result data at an expectation input of the integrated circuit chip providing the received test data to the core test inputs of each of the circuitry cores;
- generating, in each circuitry core, test result data according to the received test data, and outputting the generated test result data at a core output of the respective circuitry core;
- generating mask data from the expected result data by analyzing whether the values of expected mask data remain stable during a whole clock cycle;
- receiving mask data indicating for each of the circuitry cores whether or not the comparison of the test result data with the received expected result data is to be masked;
- detecting whether or not there is a mismatch between the test result data and the expected result data by on-chip comparing the test result data of each of the circuitry cores with the expected result data;
- and
- on-chip storing, for each of the at least two circuitry cores, in a memory a mismatch indication indicating whether or not there is a detected mismatch.
Dependencies are inferred from the claim text.