Test control circuit and semiconductor memory device including the same
AssigneeHynix Semiconductor Inc.
InventorWoo Hyun Seo
Life of this patent
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Abstract
The present invention relates to a test control circuit controlling a test of an internal circuit and a semiconductor memory device including the same. The present invention provides a test control circuit having: an encoding unit encoding test mode signals input from the external and transferring them to global lines; a decoding unit decoding the signals transferred from the global lines; and a test mode enable signal generating circuit generating test mode enable signals controlling a test mode enable by combining the output signals of the decoding unit and an address designating a test mode item code.
Claims20
A test control circuit comprising:
- an encoding unit encoding test mode signals input from an external source and transferring the encoded test mode signals to global lines;
- a decoding unit decoding the signals transferred from the encoding unit through the global lines;
- and
- a test mode enable signal generating circuit generating test mode enable signals controlling a test mode enable wherein the test mode enable responding to the output signals from the decoding unit and responding to internal addresses.
A test control circuit comprising:
- an address buffer buffering external addresses and providing external addresses to internal addresses;
- a coding unit outputting test mode signals input from the external source in response to control signals;
- and
- a test mode enable signal generating circuit generating test mode enable signals controlling a test mode enable by combining the output signals from the coding unit with an address designating a test mode item code.
A semiconductor memory device comprising:
- an encoding unit arranged in a peripheral circuit region, and encoding test mode signals input from an external source, respectively, and transferring the encoded test mode signals to global lines;
- a decoder arranged in the peripheral circuit region, and decoding some of the encoded test mode signals transferred from the global lines;
- a test mode enable generator arranged in the peripheral circuit region, and generating test mode enable signals in response to output signals from the decoder and in response to internal addresses;
- and
- a peripheral circuit arranged in the peripheral circuit region, and controlling a test with the test mode enable signals.
A semiconductor memory device comprising:
- an encoding unit arranged in a peripheral circuit region, and the encoding unit encoding test mode signals input from an external source and transferring the encoded test mode signals to a global line;
- a decoder arranged in a core region, and the decoder receiving some of the encoded test mode signals transferred from the global lines through a local line and decoding the encoded test mode signals;
- a second test mode enable generator arranged in the core region, and the second test mode enable generator generating test mode enable signals in response to output signals of the decoder and in response to internal addresses;
- and
- a core circuit arranged in the core region, and controlling a test in response to the second test mode enable signals.
Dependencies are inferred from the claim text.