Repair of memory hard failures during normal operation, using ECC and a hard fail identifier circuit

A memory sub-system operation method, comprising:

• providing a memory sub-system which includes a main memory, an ECC (Error Correction Code) circuit electrically coupled to the main memory, and a hard fail identifier circuit electrically coupled to the ECC circuit;
• said ECC circuit detecting a first bit fail at a first bit location and at a first location address of the main memory and sending an error flag signal to the hard fail identifier circuit to notify the hard fail identifier circuit about the first bit fail;
• in response to receiving the error flag signal sent by the ECC circuit, said hard fail identifier circuit generating a threshold reached signal to indicate that the first bit fail is a hard fail,
• wherein the hard fail identifier circuit comprises a failure stack electrically coupled to the ECC circuit, said failure stack comprising N entries, N being a positive integer, each entry of the N entries comprising a use bit, an address field, an age field, and a bit location field, said N entries comprising M unavailable entries and P available entries, M and P being non-negative integers, M plus P being equal to N, each unavailable entry of the M unavailable entries storing a bit fail.

A memory sub-system, comprising:

• a main memory;
• an ECC (Error Correction Code) circuit electrically coupled to the main memory;
• a hard fail identifier circuit electrically coupled to the ECC circuit;
• a repair circuit electrically coupled to the hard fail identifier circuit;
• a redundant memory electrically coupled to the main memory and the repair circuit;
• and
• a threshold setting circuit electrically coupled to the hard fail identifier circuit,
• wherein the ECC circuit is configured to detect a first bit fail at a first bit location at a first location address of the main memory,
• wherein the ECC circuit is further configured to send an error flag signal to the hard fail identifier circuit to notify the hard fail identifier circuit about the first bit fail,
• wherein the hard fail identifier circuit is configured to, in response to the error flag signal being sent, determine and track the number of times of failure occurring at the first location address and the first bit location,
• wherein the hard fail identifier circuit is further configured to determine whether the number of times of failure at the first location address and the first bit location is equal to a predetermined threshold value,
• wherein the hard fail identifier circuit is further configured to, in response to the hard fail identifier circuit determining that the number of times of failure is equal to the predetermined threshold value, generate a threshold reached signal to indicate that the first bit fail is a hard fail,
• wherein the repair circuit is configured to, in response to the threshold reached signal being generated, determine whether there is an available redundant memory location in the redundant memory,
• wherein the repair circuit is further configured to, in response to the repair circuit determining that there is an available redundant memory location in the redundant memory, select the available redundant memory location of the redundant memory to replace a defective main memory location of the main memory at the first location address, such that whenever the first location address of the first bit fail appears on an address bus of the main memory, the selected redundant memory location is accessed instead of the defective main memory location of the main memory, and
• wherein the threshold setting circuit is configured to provide the predetermined threshold value to the hard fail identifier circuit, and
• wherein the hard fail identifier circuit comprises a failure stack electrically coupled to the ECC circuit, said failure stack comprising N entries. N being a positive integer, each entry of the N entries comprising a use bit, an address field, an age field, and a bit location field, said N entries comprising M unavailable entries and P available entries, M and P being non-negative integers, M plus P being equal to N, each unavailable entry of the M unavailable entries storing a bit fail.