System and method for on-board timing margin testing of memory modules

A memory module comprising:

• a plurality of memory devices;
• and
• a memory hub, comprising:
• a link interface for receiving memory requests for access to at least one of the memory devices;
• a self-test module coupled to the at least one memory device, the self-test module operable to transmit a test signal to the at least one of memory devices, receive a responsive signal from the at least one memory device, and determine a test result indicative of whether the at least one memory device responded correctly to the test signal, the test result comprising a frequency at which the at least one memory device operates correctly;
• and
• a first bus coupled between the memory module and the at least one memory device.

A memory module comprising:

• a plurality of memory devices;
• and
• a memory hub, comprising:
• a link interface for receiving memory requests for access to at least one of the memory devices;
• a self-test module coupled to the at least one memory device, the self-test module operable to transmit a test signal to the at least one of memory devices, receive a responsive signal from the at least one memory device, and determine a test result indicative of whether the at least one memory device responded correctly to the test signal, the test result comprising a timing skew at which the at least one memory device operates correctly;
• and
• a first bus coupled between the memory module and the at least one memory device.

A memory module comprising:

• a plurality of memory devices;
• and
• a memory hub, comprising:
• a link interface for receiving memory requests for access to at least one of the memory devices;
• a self-test module coupled to the at least one memory device the self-test module operable to transmit a test signal to the at least one of memory devices, receive a responsive signal from the at least one memory device, and determine a test result indicative of whether the at least one memory device responded correctly to the test signal, wherein the test signal is not carried on a bus other than the first bus;
• and
• a first bus coupled between the memory module and the at least one memory device.

A memory module comprising:

• a plurality of memory devices;
• and
• a memory hub, comprising:
• a link interface for receiving memory requests for access to at least one of the memory devices;
• a self-test module coupled to the at least one memory device, the self-test module operable to transmit a test signal comprising a series of corresponding first and second signals to the at least one of memory devices, wherein transmitting the test signal comprises coupling the series of corresponding first and second signals to the at least one memory device and altering the relative timing between when some of the corresponding first and second signals in the series are coupled to the at least one memory device, the self-test mode further operable to receive a responsive signal from the at least one memory device, and determine a test result indicative of whether the at least one memory device responded correctly to the test signal;
• and
• a first bus coupled between the memory module and the at least one memory device.

A memory module comprising:

• a plurality of memory devices;
• and
• a memory hub comprising:
• a link interface for receiving memory requests for access to at least one of the memory devices;
• a clock generator operable to produce and couple to the at least one memory device a clock signal having a frequency;
• a self-test module coupled to the at least one memory device and the clock generator, the self-test module operable to transmit a test signal to the at least one of memory devices, receive a responsive signal from the at least one memory device, and determine a test result indicative of whether the at least one memory device responded correctly to the test signal, the self-test module being further operable to vary the frequency of the clock signal over a range, the test signal comprising a series of first input signals and the responsive signal comprising a respective series of output signals from the at least one memory device, and the test result comprising an indicator of whether the at least one memory device properly responded to the series of first signals as the frequency of the clock signal is varied;
• and
• a first bus coupled between the memory module and the at least one memory device.

A processor-based system, comprising:

• a processor having a processor bus;
• a system controller coupled to the processor bus, the system controller having a system memory port and a peripheral device port;
• and
• a memory module coupled to the system memory port of the system controller, the memory module comprising:
• a plurality of memory devices;
• and
• a memory hub, comprising:
• a link interface for receiving memory requests for access to at least one of the memory devices;
• a self-test module coupled to the at least one memory device, the self-test module operable to transmit a test signal to the at least one of memory devices on a first bus receive a responsive signal from the at least one memory device, and determine a test result indicative of whether the at least one memory device responded correctly to the test signal;
• and
• a second bus coupled between the memory hub and the at least one memory device, the second bus being different from the first bus.

A method for testing in a memory system having a memory hub coupled to a plurality of memory devices, the method comprising:

• generating testing signals in the memory hub;
• coupling the testing signals from the memory hub to the memory devices and varying the relative timing between when the test signals are applied to the memory devices;
• generating output signals in the memory devices resulting from the testing signals;
• coupling the output signals from the memory devices to the memory hub;
• and
• evaluating the output signals in the memory hub to determine if the memory devices properly responded to the test signals.

A method for testing in a memory system having a memory hub coupled to a plurality of memory devices, the method comprising:

• generating testing signals in the memory hub, wherein the testing signals comprise a clock signal having a variable frequency;
• altering the frequency of the clock signal;
• coupling the testing signals from the memory hub to the memory devices responsive to the clock signal;
• generating output signals in the memory devices resulting from the testing signals;
• coupling the output signals from the memory devices to the memory hub;
• and
• evaluating the output signals in the memory hub to determine if the memory devices properly responded to the test signals.