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US 7,689,878 B2Granted
System and method for testing defects in an electronic circuit
AssigneeNXP B.V.
InventorMohamed Azimane
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AssigneeNXP B.V.
InventorMohamed Azimane
Estimating the term…
A new test pattern which consists of performing “very small jumps” and “very big jumps” within the matrix. The “very small jumps” are controlled by the row decoder, and have the effect of sensitizing the resistive open defects which lead to slow-to-fall behavior in the word line. A “very small jump” means that the memory position of two consecutive accesses remains in a unique sub-cluster until all rows in that sub-cluster have been tested, remains in the same cluster until all rows in that cluster have been tested, remains in the same U section until all rows in that U section have been tested, and finally, remains in the same Z block until all of the rows of that Z block have been tested. The “very big jumps” are intended to cover the class of resistive open defects which leads to slow-to-rise behavior, and is intended to mean that two consecutive memory accesses must never stay in the same subcluster, at the same cluster, or at the same U section.
A method for testing an electronic circuit that includes a matrix of cells for receiving logic data, said matrix of cells being divided into a plurality of Z blocks each comprising n rows of cells, where n is an integer >1, each Z block is divided into a plurality of U sections, each including some of the n rows of the respective Z block, each U section is divided into a plurality of clusters, each including some of the rows of the respective U section, the method comprising:
An apparatus for testing an electronic circuit that includes a matrix of cells for receiving logic data, said matrix of cells being divided into a plurality of Z blocks each including n rows of cells, where n is a integer greater than 1, each of said Z blocks being divided into a plurality of U sections, each including some of the n rows of the respective Z block, the apparatus comprising
A method for testing an electronic circuit that includes a matrix of cells for receiving logic data, said matrix of cells being divided into a plurality of Z blocks each including n rows of cells, where n is an integer >1, each of said Z blocks being divided into a plurality of U sections, each including some of the n rows of the respective Z block, the method comprising
Dependencies are inferred from the claim text.