Back to results
US 7,689,867 B2Granted
Multiprocessor breakpoint
AssigneeIntel Corporation
InventorsMark B. Rosenbluth, Xiao-Feng Li, Dz-ching (Roy) Ju, Aaron R. Kunze
Life of this patent
Estimating the term…
Abstract
Techniques that may be utilized in a multiprocessor system are described. In one embodiment, one or more signals are generated to indicate that a breakpoint instruction is executed by one of the plurality of processors in the multiprocessor system. For example, a signal may be generated to indicate whether a processor is to be halted once it receives the a signal that indicates the breakpoint instruction. Other embodiments are also disclosed.
Claims23
An apparatus comprising:
- a first logic to generate a first signal indicative of execution of a breakpoint instruction by a processor of a multiprocessor system;
- and
- a second logic to generate a second signal, in response to the first signal, indicative of execution of the breakpoint instruction to one or more processors of the multiprocessor system, wherein the processor comprises a third logic to generate a third signal indicative of whether the processor is to be halted once it receives the second signal, wherein the second logic is to generate the second signal independent of an execution state of the one or more processors of the multiprocessor system.
A method comprising:
- generating a first signal in response to execution of a breakpoint instruction by a processor of a multiprocessor system;
- generating a second signal, in response to the first signal, indicative of execution of the breakpoint instruction to one or more processors of the multiprocessor system;
- generating a third signal indicative of whether the processor is to be halted once it receives the second signal;
- and
- generating the second signal independent of an execution state of the one or more processors of the multiprocessor system.
2 more elements
A system comprising:
- a volatile memory to store a breakpoint instruction;
- and
- a multiprocessor system that comprises:
- a first logic to generate a first signal indicative of execution of the breakpoint instruction by a processor of the multiprocessor system;
- and
- a second logic to generate a second signal, in response to the first signal, indicative of execution of the breakpoint instruction to one or more processors of the multiprocessor system independent of an execution state of the one or more processors of the multiprocessor system, wherein the processor comprises a third logic to generate a third signal indicative of whether the processor is to be halted once it receives the second signal.
3 more elements
Dependencies are inferred from the claim text.