Synchronization of network communication link
AssigneeIntel Corporation
InventorDean S. Susnow
Life of this patent
Estimating the term…
Abstract
Commands are passed between first and second asynchronous clock domains. Unique coded command signals are inserted into a data stream transmitted from the first asynchronous clock domain to the second asynchronous clock domain. They are passed without change from the first asynchronous clock domain to the second asynchronous clock domain through an elastic buffer. The unique coded command signals are then decoded in receiver circuitry in the second asynchronous clock domain. Process circuitry in the second asynchronous clock domain is controlled according to the decoded command signals.
Claims9
A method comprising:
- inserting coded command signals into a data stream transmitted from a first asynchronous clock domain to a second asynchronous clock domain, wherein the coded command signals implement link synchronization for data being transmitted from the first asynchronous clock domain to the second asynchronous clock domain;
- passing the coded command signals without change from the first asynchronous clock domain to the second asynchronous clock domain through an elastic buffer, wherein the passing of the coded command signals is independent of the use of an asynchronous sideband signal;
- decoding the coded command signals in a receiver in the second asynchronous clock domain to generate decoded command signals;
- and
- controlling a transmitter in the second asynchronous clock domain according to the decoded command signals, wherein the decoded command signals are to instruct the transmitter to transmit a sequence of one or more IDLE characters into the data stream.
An apparatus comprising:
- a physical logic block to receive data from a network link, wherein the physical logic block is to operate in a link clock domain;
- an elastic buffer to receive the data from the physical logic block in the link clock domain and to output data in a core clock domain;
- a receiver logic block to extract the data from the elastic buffer and to decode synchronous command signals in the core clock domain relating to link synchronization between the link clock domain and the core clock domain;
- and
- a transmitter logic block to transmit signals to establish the link synchronization according to a control signal received from the receiver logic block, wherein the control signal is based on the synchronous command signals, wherein the control signal is to instruct the transmitter logic block to transmit a sequence of one or more IDLE characters into the data, wherein the data is received independent of the use of an asynchronous sideband signal.
Dependencies are inferred from the claim text.